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w wm8991 mobile multimedia codec with dual-mode class ab/d speaker driver wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, december 2008, rev 4.0 copyright ? 2008 wolfson microelectronics plc description the wm8991 is a highly integrated ultra-low power hi-fi codec designed for handsets rich in multimedia features such as mobile tv, digital audio playback and gaming. ultra-low power and low noise interfaces to many other audio components in the system are provided. a powerful 1w speaker driver can operate in class d or ab modes, providing total flexibility to the system designer. low leakage, high psrr and pop/click suppression enable direct battery connection for the speaker supply. a very highly flexible input configuration supports multiple microphone or line inputs (mono or stereo, single-ended or differential). four headphone drivers support fully differential headset drive, providing excellent crosstalk performance and bass response, maximising stereo effects, and allowing the removal of large and expensive headphone capacitors. stereo 24-bit sigma-delta adcs and dacs provide hi-fi quality audio record and playback, with a flexible digital audio interface supporting most commonly-used clocking schemes. an integrated low power pll, an alternative dac interface and tdm support provide additional flexibility. the wm8991 is supplied in very small and thin 5x5mm 65-ball bga package, ideal for use in portable systems. features dac snr 99db (?a? weighted), thd -84db at 48khz, 3.3v adc snr 94db (?a? weighted), thd -82db at 48khz, 3.3v microphone interface (up to four differential microphones) 1w speaker driver - 1w into 8 btl speaker at <0.1% thd - 80db psrr @217hz - <1ua leakage with direct battery connection - software-selectable class d or ab mode - filterless connection supported - pop/click suppression headphone / ear speaker drivers - 40mw output power into 16 at 3.3v - fully differential and capless modes supported - pop/click suppression 4 mono or stereo differential line outputs powerful gpio functions ultra-low power consumption - 8.3mw analogue voice call - 13.7mw dac playback to headphones on-chip pll provides flexible clocking scheme sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48khz 65-ball 5x5mm bga package applications multimedia phones gps
wm8991 production data w pd, december 2008, rev 4.0 2 table of contents description ....................................................................................................... 1 features............................................................................................................. 1 applications ..................................................................................................... 1 table of contents ......................................................................................... 2 block diagram ................................................................................................. 4 pin configuration ........................................................................................... 5 ordering information .................................................................................. 5 pin description ................................................................................................ 6 absolute maximum ratings ......................................................................... 8 recommended operating conditions ..................................................... 8 speaker power de-rating curve ............................................................ 10 electrical characteristics .................................................................... 12 typical power consumption .................................................................... 24 speaker driver performance ................................................................. 25 headphone driver performance ............................................................ 25 psrr performance ....................................................................................... 26 audio signal paths ....................................................................................... 28 signal timing requirements ..................................................................... 29 system clock timing ............................................................................................ 29 test conditions .................................................................................................... 29 audio interface timing ? master mode ......................................................... 30 audio interface timing ? slave mode ............................................................ 31 audio interface timing ? tdm mode ................................................................ 32 control interface timing ? 2-wire mode ..................................................... 33 control interface timing ? 3-wire mode ..................................................... 34 control interface timing ? 4-wire mode ..................................................... 35 internal power on reset circuit .......................................................... 36 device description ....................................................................................... 38 introduction .......................................................................................................... 38 input signal path .................................................................................................. 39 analogue to digital converter (adc) .......................................................... 54 digital mixing ......................................................................................................... 57 digital to analogue converter (dac) .......................................................... 61 output signal path .............................................................................................. 65 analogue outputs ............................................................................................... 76 thermal shutdown .............................................................................................. 81 general purpose input/output ...................................................................... 82 digital audio interface .................................................................................... 101 digital audio interface control ................................................................. 113 clocking and sample rates ............................................................................ 119 control interface ............................................................................................ 127 power management ........................................................................................... 131 pop suppression control............................................................................... 134 power domains .................................................................................................... 139 register map ................................................................................................. 140 register bits by address ........................................................................ 142
production data wm8991 w pd, december 2008, rev 4.0 3 digital filter characteristics ............................................................. 166 adc filter responses ....................................................................................... 167 adc high pass filter responses ................................................................... 167 dac filter responses ....................................................................................... 168 de-emphasis filter responses ...................................................................... 169 applications information ....................................................................... 170 recommended external components ......................................................... 170 package dimensions .................................................................................. 173 important notice ........................................................................................ 174 address: ................................................................................................................. 174
wm8991 production data w pd, december 2008, rev 4.0 4 block diagram control interface sdin sclk adcdat adclrc/gpio1 bclk dacdat daclrc mode csb/addr gpio5/dacdat2 gpio6/adclrcb digital audio interface a-law and u-law support tdm support dcvdd dbvdd dgnd spkgnd spkvdd hpvdd hpgnd gpio2/mclk2 gpio3/bclk2 gpio4/daclrc2 mclk pll sysclk mclk2 mclk left adc bypass left mic left line input to left output mixer rx voice - left line input to speaker right line input to speaker rx voice + right line input to right output mixer right mic right adc bypass input pgas input mixers digital core gpio alternative dac interface alternative mclk button control / accessory detect clock output inverted adclrc micbias 50k 50k v ref avdd agnd vmid lin2 lin1 rin1 lin3/gpi7 rin3/gpi8 rin2 lin4/rxn rin4/rxp + - + - + - + - + - inmixr lin12 lin34 rin34 rin12 ainlmux ainrmux en + - 250k 250k 5k 5k micbias current detect -73db to +6db, 1db steps -73db to +6db, 1db steps + + + + lin2 mixer l dac l dac r mixer r rin2 lin3 l mic r mic r adc bypass l adc bypass dac l dac r r adc bypass l adc bypass l mic r mic rin3 mixer r rxp rxn mixer l mic l mic r mixer l mixer r mic l mic r inverted out r mixer l mixer r inverted out l output mixers lopga ropga high pass filter (voice or hi-fi) high pass filter (voice or hi-fi) + 0db, +6db, +12db, +18db 0 0 adc l adc r + mono mix -71.625db to +17.625db, 0.375db steps -71.625db to +17.625db, 0.375db steps -71.625db to 0db, 0.375db steps -71.625db to 0db, 0.375db steps -36db to 0db, 3db steps -12db to 0db, 3db steps -12db to 0db, 3db steps 0db, +30db 0db, +30db -12db to +6db -12db to +6db 0db, +30db 0db, +30db -12db to +6db -12db to +6db -16.5db to +30db, 0.75db steps -16.5db to +30db, 0.75db steps -16.5db to +30db, 0.75db steps -16.5db to +30db, 0.75db steps diffinl diffinr out3mix out4mix ropmix ronmix lonmix lopmix dac l dac r + inmixl + + por avdd dcvdd por -12db to +6db - + rxvoice - + -12db to +6db -12db to +6db -12db to +6db rxvoice rin3 lin3 lomix + romix + record r record l ladc bypass radc bypass + mixer l + mixer r spkmix + 0db, -6db, -12db lout out3 out4 lon lop rop ron hp -73db to +6db, 1db steps hp rout -73db to +6db, 1db steps hp hp line line line line 0db, -6db 0db, -6db 0db, -6db 0db, -6db -1 -1 spkp spkn spk 1x, 1.27x, 1.4x, 1.52x, 1.67x 1.8x 1xvmid, 1.27xvmid, 1.4xvmid, 1.52xvmid, 1.67xvmid 1.8xvmid spkpga -73db to +6db, 1db steps w wm8991
production data wm8991 w pd, december 2008, rev 4.0 5 pin configuration agnd dgnd mode lin3/ gpi7 lin4/ rxn spk gnd spkn lin1 spkn agnd rin3/ gpi8 rop lin2 rin1 rin2 agnd agnd lop agnd spkp avdd out4 out3 agnd mic bias spkp avdd hpvdd hpvdd hpgnd hpgnd agnd spk vdd spk vdd dcvdd nc nc adc lrc/ gpio1 gpio2/ mclk2 csb/ addr sdin dbvdd mclk bclk adc dat dac dat gpio3/ bclk2 gpio4/ dac lrc2 gpio5/ dac dat2 gpio6/ adc lrcb rin4/ rxp agnd agnd agnd agnd rout lout vmid spk gnd lon ron sclk n/c dac lrc dgnd 19 8 7 6 5 4 3 2 a j h g f e d c b ordering information order code temperature range package moisture sensitivity level peak soldering temperature wm8991geb/v -40 c to +85 c 65-ball bga (pb-free) msl3 260 c wm8991geb/rv -40 c to +85 c 65-ball bga (pb-free, tape and reel) msl3 260 c note: reel quantity = 3500
wm8991 production data w pd, december 2008, rev 4.0 6 pin description pin no name type description b8 micbias analogue output microphone bias d1 lin1 analogue input left channel single-ended mic input / left channel negative differential mic input d2 lin2 analogue input left channel line input / left channel positive differential mic input c1 lin3 / gpi7 analogue input / digital input left channel line input / left channel negative differential mic input / accessory or button detect input pin c2 lin4 / rxn analogue input left channel line input / left channel positive differential mic input / mono differential negative input (rx voice -) e1 rin1 analogue input right channel single-ended mic input / right channel negative differential mic input e2 rin2 analogue input right channel line input / right channel positive differential mic input f1 rin3 / gpi8 analogue input / digital input right channel line input / right channel negative differential mic input / accessory or button detect input pin f2 rin4 / rxp analogue input left channel line input / left channel positive differential mic input / mono differential positive input (rx voice +) h1 dcvdd supply digital core supply g1 g2 dgnd supply digital ground (return path for both dcvdd and dbvdd) j1 dbvdd supply digital buffer (i/o) supply a1 b1 avdd supply analogue supply a6 b6 d4 d5 d6 e4 e5 e6 f4 f5 f6 agnd supply analogue ground (return path for avdd) note: d4 to f6 are gnd_paddles for thermal conduction and must be connected on the pcb for thermal reasons. a2 a3 hpvdd supply headphone supply a4 a5 hpgnd supply headphone ground (return path for hpvdd) a7 a8 spkvdd supply supply for speaker driver c8 d8 spkgnd supply ground for speaker driver (return path from s pkvdd) j2 mclk digital input master clock j3 bclk digital input / output audio interface bit clock h5 daclrc digital input / output audio interface dac left / right clock j5 dacdat digital input dac digital audio data h4 adclrc / gpio1 digital input / output audio interface adc left / right clock / gpio1 pin j4 adcdat digital output adc digital audio data
production data wm8991 w pd, december 2008, rev 4.0 7 pin no name type description g8 mode digital input selects 2-wire or 3/4 -wire control h9 csb / addr digital input 3/4 -wire chip select or 2-wire address select g9 sclk digital input control interface clock input h8 sdin digital input / output control interface data input / 2-wire acknowledge output a9 b9 spkp analogue output speaker positive output c9 d9 spkn analogue output speaker negative output b5 lout analogue output left headphone output b2 rout analogue output right headphone output b4 out3 analogue output inverted left headphone output / mono inverted output b3 out4 analogue output inverted right headphone output / mono non-inverted output e8 lon analogue output negative left line output / positive right line output e9 lop analogue output positive left line output f8 ron analogue output negative right line output / positive left line output f9 rop analogue output positive right line output b7 vmid analogue output mid-rail voltage decoupling capacitor j6 gpio2 / mclk2 digital input / output alternative mclk / gpio pin h6 gpio3 / bclk2 digital input / output alternative bclk / gpio pin j7 gpio4 / daclrc2 digital input / output alternative daclrc / gpio pin h7 gpio5 / dacdat2 digital input / output alternative dacdat / gpio pin j8 gpio6 / adclrcb digital input / output inverted adclrc / gpio pin h2 h3 j9 nc not connected
wm8991 production data w pd, december 2008, rev 4.0 8 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max supply voltages (excluding spkvdd) -0.3v +4.5v spkvdd -0.3v +7v voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a -40oc +85oc junction temperature, t jmax -40oc +150oc storage temperature after soldering -65oc +150oc recommended operating conditions parameter symbol min typ max unit digital supply range (core) dcvdd 1.71 3.6 v digital supply range (buffer) dbvdd 1.71 3.6 v analogue supplies range avdd, hpvdd 2.7 3.6 v speaker supply range spkvdd 2.7 5.5 v ground dgnd, agnd, hpgnd, spkgnd 0 v notes 1. analogue, digital and speaker grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely independent from each other (i.e. not internally connected). 3. dcvdd must be less than or equal to avdd. 4. dcvdd must be less than or equal to dbvdd. 5. avdd must be less than or equal to spkvdd. 6. spkvdd must be high enough to support the peak output voltage when using dcgain and acgain functions, to avoid output waveform clipping. peak output voltage is avdd*(dcgain+acgain)/2. 7. hpvdd must be equal to avdd
production data wm8991 w pd, december 2008, rev 4.0 9 thermal performance thermal analysis should be performed in the intended application to prevent the wm8991 from exceeding maximum junction temperature. several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device on the pcb in relation to surrounding components and the number of pcb layers. connecting the gnd balls through thermal vias and into a large ground plane will aid heat extraction. three main heat transfer paths exist to surrounding air as illustrated below in figure 1: - package top to air (radiation). - package bottom to pcb (radiation). - package balls to pcb (conduction). figure 1 heat transfer paths the temperature rise t r is given by t r = p d * ? ja - p d is the power dissipated in the device. - ? ja is the thermal resistance from the junction of the die to the ambient temperature and is therefore a measure of heat transfer from the die to surrounding air. ? ja is determined with reference to jedec standard jesd51-9. the junction temperature t j is given by t j = t a +t r , where t a is the ambient temperature. parameter symbol min typ max unit operating temperature range t a -40 85 c operating junction temperature t j -40 100 c thermal resistance ? ja 57 c/w
wm8991 production data w pd, december 2008, rev 4.0 10 speaker power de-rating curve the speaker driver has been designed to drive a maximum of 1w into 8 with a 5v supply. however, thermal restrictions defined by the bga package ? ja limit the amount of power that can be safely dissipated in the device without exceeding the maximum operating junction temperature. power dissipated in the device correlates directly with speaker efficiency, hence there are separate de-rating curves for class d and class ab operation. under no circumstances should the recommended maximum powers be exceeded. class d de-rating curves the de-rating curves shown in figure 2 are based on a full scale sinusoidal input. p [w] t [oc] 80 70 60 0.4 0.6 0.8 1.0 spkvdd = 2.7v spkvdd = 3v spkvdd = 3.3v spkvdd = 3.6v spkvdd = 4.2v spkvdd = 5v spkvdd = 5.5v 0.9 0.7 0.3 0.5 0.1 0.2 55 65 75 85 figure 2 class d speaker power de-rating curve
production data wm8991 w pd, december 2008, rev 4.0 11 class ab de-rating curve the de-rating curves shown in figure 3 are based on a full scale sinusoidal input p [w] t [oc] 80 70 60 0.4 0.6 0.8 1.0 spkvdd = 2.7v spkvdd = 3v spkvdd = 3.3v spkvdd = 3.6v spkvdd = 4.2v spkvdd = 5v spkvdd = 5.5v 0.9 0.7 0.3 0.5 0.1 0.2 55 65 75 85 figure 3 class ab speaker power de-rating curve
wm8991 production data w pd, december 2008, rev 4.0 12 electrical characteristics test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit analogue input pin maximum signal levels (lin1, lin2, lin3, lin4, rin1, rin2, rin3, rin4) a1 maximum full-scale pga input signal level note 1: this changes in proportion to avdd (avdd/3.3). note 2: when mixing input pga outputs and line inputs the total signal must not exceed 1vrms (0dbv). note 3: a 1.0vrms differential signal equates to 0.5vrms/-6dbv per input. single-ended pga input on lin1, lin3, rin1 or rin3, output to inmixl or inmixr 1.0 0 vrms dbv differential pga input on lin1/lin2, lin3/lin4, rin1/rin2 or rin3/rin4, output to inmixl or inmixr 1.0 0 vrms dbv differential input to two single-ended pga inputs on lin1/lin3 or rin1/rin3, output to diffinl or diffinr 1.0 0 vrms dbv a2 maximum full-scale line input signal level note 1: this changes in proportion to avdd (avdd/3.3). note 2: when mixing line inputs, input pga outputs and dac outputs the total signal must not exceed 1vrms (0dbv). note 3: a 1.0vrms differential signal equates to 0.5vrms/-6dbv per input. line input on lin2, lin4, rin2 or rin4 to inmixl or inmixr 1.0 0 vrms dbv line input on lin2 or rin2 to spkmix 1.0 0 vrms dbv line input on lin3 or rin3 to lomix or romix 1.0 0 vrms dbv differential mono line input on rxp/rxn to rxvoice 1.0 0 vrms dbv differential mono line input on rxp/rxn to differential output on out3/out4 1.0 0 vrms dbv
production data wm8991 w pd, december 2008, rev 4.0 13 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit analogue input pin impedances (lin1, lin2, lin3, lin4, rin1, rin2, rin3, rin4) b1 pga input resistance note: this will be seen in parallel with the resistance of other enabled input paths from the same pin lin1, lin3, rin1 or rin3 (pga gain = -16.5db) 57 k lin1, lin3, rin1 or rin3 (pga gain = 0db) 33 k lin1, lin3, rin1 or rin3 (pga gain = +30db) 2 k lin2, lin4, rin2 or rin4 (constant for all gains) 65 k b2 line input resistance note: this will be seen in parallel with the resistance of other enabled input paths from the same pin lin2 or rin2 to inmixl or inmixr (-12db) 60 k lin2 or rin2 to inmixl or inmixr (0db) 15 k lin2 or rin2 to inmixl or inmixr (+6db) 7.5 k lin2 or rin2 to spkmix (spkattn = 0db) 20 k lin2 or rin2 to spkmix (spkattn = -12db) 20 k lin3 or rin3 to lomix or romix (0db) 20 k lin3 or rin3 to lomix or romix (-21db) 224 k rxp and rxn via rxvoice to ainlmux or ainrmux (gain = +6db) 7.5 k rxp and rxn via rxvoice to ainlmux or ainrmux (gain = 0db) 15 k rxp and rxn via rxvoice to ainlmux or ainrmux (gain = -12db) 45 k rxp and rxn via rxvoice to ainlmux and ainrmux (gain = +6db) 3.8 k rxp and rxn via rxvoice to ainlmux and ainrmux (gain = 0db) 7.5 k rxp and rxn via rxvoice to ainlmux and ainrmux (gain = -12db) 25 k lin4 to out3 or rin4 to out4 (gain = -6db) 20 k lin4 to out3 or rin4 to out4 (gain = 0db) 20 k b3 input capacitance all analogue input pins 10 pf
wm8991 production data w pd, december 2008, rev 4.0 14 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit input programmable gain amplifiers (pgas) lin12, lin34, rin12 and rin34 c1 minimum programmable gain -16.5 db c2 maximum programmable gain 30 db c3 programmable gain step size guaranteed monotonic 1.5 db c4 mute attenuation inputs disconnected 90 db c5 common mode rejection ratio (1khz input) single pga in differential mode, gain = +30db 60 db single pga in differential mode, gain = 0db 50 single pga in differential mode, gain = -16.5db 50 differential input to diffinl or diffinr via lin1/lin3 or rin1/rin3, gain = 0db 45 received voice (rxp-rxn) differential to single-ended converter rxvoice c6 minimum programmable gain ainlmode = 01 or ainrmode = 01 -12 db c7 maximum programmable gain ainlmode = 01 or ainrmode = 01 +6 db c8 programmable gain step size ainlmode = 01 or ainrmode = 01 3 db c9 mute attenuation ainlmode = 01 or ainrmode = 01 95 db pga output differential to single ended converters diffinl and diffinr c10 fixed gain ainlmode = 10 or ainrmode = 10 0 db c11 mute attenuation ainlmode = 10 or ainrmode = 10 95 db input mixers inmixl and inmixr c12 minimum programmable gain pga outputs to inmixl and inmixr 0 db c13 maximum programmable gain pga outputs to inmixl and inmixr +30 db c14 programmable gain step size pga outputs to inmixl and inmixr 30 db c15 minimum programmable gain line inputs and record path to inmixl and inmixr -12 db c16 maximum programmable gain line inputs and record path to inmixl and inmixr +6 db c17 programmable gain step size line inputs and record path to inmixl and inmixr 3 db c18 mute attenuation 95 db output programmable gain amplifiers (pgas) spkpga, lopga, ropga, lout and rout c19 minimum programmable gain -73 db c20 maximum programmable gain +6 db c21 programmable gain step size guaranteed monotonic 1 db c22 mute attenuation lout and rout 80 db spkpga, lopga and ropga 70 db output programmable gain amplifiers (pgas) out3, out4, lop and rop c23 minimum programmable gain -6 db c24 maximum programmable gain 0 db c25 programmable gain step size 6 db c26 mute attenuation out3 and out4 80 db lop and rop (also applies to lon and ron) 100 db speaker attenuation (spkattn) c27 minimum programmable gain -12 db c28 maximum programmable gain 0 db c29 programmable gain step size 6 db c30 mute attenuation 80 db
production data wm8991 w pd, december 2008, rev 4.0 15 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit adc input path performance d1 snr (a-weighted) line inputs to adc via inmixl and inmixr, avdd = 3.3v 84 94 db thd (-1dbfs input) -84 -75 db thd+n (-1dbfs input) -82 -73 db crosstalk (l/r) -100 db avdd psrr (217hz) 45 db dcvdd psrr (217hz) 80 db snr (a-weighted) line inputs to adc via inmixl and inmixr, avdd = 2.7v 93 db thd (-1dbfs input) -78 db thd+n (-1dbfs input) -76 db d2 snr (a-weighted) record path (dacs to adcs via inmixl and inmixr), avdd = 3.3v 93 db thd (-1dbfs input) -83 db thd+n (-1dbfs input) -81 db crosstalk (l/r) -95 db snr (a-weighted) record path (dacs to adcs via inmixl and inmixr), avdd = 2.7v 92 db thd (-1dbfs input) -78 db thd+n (-1dbfs input) -76 db d3 snr (a-weighted) input pgas to adc via inmixl or inmixr, avdd = 3.3v 84 94 db thd (-1dbfs input) -84 -75 db thd+n (-1dbfs input) -82 -73 db crosstalk (l/r) -100 db avdd psrr (217hz) 45 db snr (a-weighted) input pgas to adc via inmixl or inmixr, avdd = 2.7v 92 db thd (-1dbfs input) -78 db thd+n (-1dbfs input) -76 db d4 snr (a-weighted) input pgas to adc via diffinl or diffinr, avdd = 3.3v 84 94 db thd (-1dbfs input) -82 -75 db thd+n (-1dbfs input) -80 -73 db crosstalk (l/r) -100 db snr (a-weighted) input pgas to adc via diffinl or diffinr, avdd = 2.7v 92 db thd (-1dbfs input) -73 db thd+n (-1dbfs input) -71 db d5 snr (a-weighted) rxp-rxn to one adc via rxvoice, avdd = 3.3v 94 db thd (-1dbfs input) -81 db thd+n (-1dbfs input) -79 db snr (a-weighted) rxp-rxn to one adc via rxvoice, avdd = 2.7v 92 db thd (-1dbfs input) -78 db thd+n (-1dbfs input) -76 db
wm8991 production data w pd, december 2008, rev 4.0 16 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit dac output path (line outputs 10k / 50pf load, headphone outputs 16 load, speaker output 8 btl load) e1 snr (a-weighted) dac to single- ended line out, 0dbfs input, avdd = 3.3v 99 db thd -86 db thd+n -84 db crosstalk (l/r) -100 db avdd psrr (217hz) 45 db snr (a-weighted) dac to single- ended line out, 0dbfs input, avdd = 2.7v 97 db thd -89 db thd+n -87 db e2 snr (a-weighted) dac to differential line out, 0dbfs input, avdd = 3.3v 99 db thd -86 db thd+n -84 db crosstalk (l/r) -100 db avdd psrr (217hz) 60 db dc offset at load 5 mv snr (a-weighted) dac to differential line out, 0dbfs input, avdd = 2.7v 97 db thd -90 db thd+n -88 db e3 minimum line out resistance lop, lon, rop, ron 2 k e4 maximum line out capacitance lop, lon, rop, ron 10 nf e5 snr (a-weighted) dac to lout or rout, r l =32 , avdd=hpvdd= 3.3v 32 ac-coupled headphone outputs 99 db thd (p o =20mw) -81 db thd+n (p o =20mw) -79 db thd (p o =5mw) -77 db thd+n (p o =5mw) -75 db crosstalk (l/r) -100 db avdd psrr (217hz) 45 db hpvdd psrr (217hz) 85 db snr (a-weighted) dac to lout or rout, r l =32 , avdd=hpvdd= 2.7v 97 db thd (p o =5mw) -76 db thd+n (p o =5mw) -74 db e6 snr (a-weighted) dac to lout or rout, r l =16 , avdd=hpvdd= 3.3v 16 ac-coupled headphone outputs lout or rout lomix or romix + dacl or dacr + r load = 16ohm 90 99 db thd (p o =20mw) -77 -71 db thd+n (p o =20mw) -75 -69 db thd (p o =5mw) -73 db thd+n (p o =5mw) -71 db crosstalk (l/r) -100 db avdd psrr (217hz) 45 db hpvdd psrr (217hz) 85 db snr (a-weighted) dac to lout, or rout, r l =16 , avdd=hpvdd= 2.7v 97 db thd (p o =20mw) -74 db thd+n (p o =20mw) -72 db thd (p o =5mw) -72 db thd+n (p o =5mw) -70 db
production data wm8991 w pd, december 2008, rev 4.0 17 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit e7 snr (a-weighted) dac to lout/out3 or rout/out4, r l =16 , avdd=hpvdd= 3.3v fully differential headphone outputs 99 db thd (p o =20mw) -71 db thd+n (p o =20mw) -69 db thd (p o =5mw) -67 db thd+n (p o =5mw) -65 db crosstalk (l/r) -100 db avdd psrr (217hz) 60 db hpvdd psrr (217hz) 85 db dc offset at load 5 mv snr (a-weighted) dac to lout/out3 or rout/out4, r l =16 , avdd=hpvdd= 2.7v 98 db thd (p o =20mw) -70 db thd+n (p o =20mw) -68 db thd (p o =5mw) -66 db thd+n (p o =5mw) -64 db e8 snr (a-weighted) dac to lout or rout capless (out3 or 4 as pseudo gnd), r l =16 , avdd=hpvdd= 3.3v 16 capless headphone outputs 99 db thd (p o =20mw) -73 db thd+n (p o =20mw) -71 db thd (p o =5mw) -69 db thd+n (p o =5mw) -67 db crosstalk (l/r) -45 db avdd psrr (217hz) 45 db hpvdd psrr (217hz) 85 db snr (a-weighted) dac to lout, or rout capless (out3 or 4 as pseudo gnd), r l =16 , avdd=hpvdd= 2.7v 97 db thd (p o =20mw) -70 db thd+n (p o =20mw) -68 db thd (p o =5mw) -67 db thd+n (p o =5mw) -65 db e9 minimum headphone resistance lout, rout, out3, out4 15 e10 spkvdd leakage current spkvdd=5.0v, 1 ua e11 snr (a-weighted) dac to speaker output (direct) avdd=3.3v, spkvdd=5v, class d, p o controlled using dac volume, acgain=dcga in=1.52 93 db thd (p o =0.5w) -87 db thd+n (p o =0.5w) -85 db thd (p o =1.0w) -76 db thd+n (p o =1.0w) -74 db spkvdd psrr( 217hz) 75 db snr (a-weighted) dac to speaker output (direct) avdd=3.3v, spkvdd=5v, class ab, p o controlled using dac volume 90 97 db thd (p o =0.5w) -78 -69 db thd+n (p o =0.5w) -76 -67 db thd (p o =1.0w) -76 -61 db thd+n (p o =1.0w) -74 -60 db spkvdd psrr( 217hz) 75 db dc offset at load 5 mv
wm8991 production data w pd, december 2008, rev 4.0 18 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit bypass path performance (line outputs 10k / 50pf load, headphone outputs 16 load, speaker output 8 btl load) f1 snr (a-weighted) differential input on rxp/rxn to differential output on out3/out4, avdd=hpvdd= 3.3v 110 db thd (p o =20mw) -72 db thd+n (p o =20mw) -70 db thd (p o =5mw) -68 db thd+n (p o =5mw) -66 db avdd psrr (217hz) 80 db hpvdd psrr (217hz) 90 db dc offset at load 5 mv snr (a-weighted) differential input on rxp/rxn to differential output on out3/out4, avdd=hpvdd= 2.7v 108 db thd (p o =20mw) -70 db thd+n (p o =20mw) -68 db thd (p o =5mw) -67 db thd+n (p o =5mw) -65 db f2 snr (a-weighted) rxvoice via lomix or romix to headphone outputs, avdd=hpvdd= 3.3v 100 db thd (p o =20mw) -77 db thd+n (p o =20mw) -75 db thd (p o =5mw) -73 db thd+n (p o =5mw) -71 db avdd psrr (217hz) 45 db hpvdd psrr (217hz) 85 db snr (a-weighted) rxvoice via lomix or romix to headphone outputs, avdd=hpvdd= 2.7v 98 db thd (p o =20mw) -74 db thd+n (p o =20mw) -72 db thd (p o =5mw) -72 db thd+n (p o =5mw) -70 db f3 snr (a-weighted) line input to spkmix, avdd=3.3v, spkvdd=5v, acgain= dcgain=1.52, class d mode 93 db thd (p o =0.5w) -87 db thd+n (p o =0.5w) -85 db thd (p o =1.0w) -81 db thd+n (p o =1.0w) -79 db avdd psrr (217hz) 45 db spkvdd psrr( 217hz) 80 db snr (a-weighted) line input to spkmix, avdd=3.3v, spkvdd=5v, class ab mode 91 101 db thd (p o =0.5w) -78 -69 db thd+n (p o =0.5w) -76 -67 db thd (p o =1.0w) -76 -61 db thd+n (p o =1.0w) -74 -60 db avdd psrr (217hz) 45 db spkvdd psrr( 217hz) 80 db dc offset at load 5 mv
production data wm8991 w pd, december 2008, rev 4.0 19 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit f4 snr (a-weighted) input pga to differential line out, avdd=3.3v 90 101 db thd (0db output) -99 -90 db thd+n (0db output) -97 -88 db avdd psrr (217hz) 45 db dc offset at load 5 mv snr (a-weighted) input pga to differential line out, avdd=2.7v 100 db thd (0db output) -95 db thd+n (0db output) -93 db f5 snr (a-weighted) input pga via lomix or romix to lout or rout, r l =16 , avdd=hpvdd= 3.3v 92 102 db thd (p o =20mw) -77 -71 db thd+n (p o =20mw) -75 -69 db thd (p o =5mw) -73 db thd+n (p o =5mw) -71 db avdd psrr (217hz) 45 db hpvdd psrr (217hz) 85 db crosstalk (l/r) -95 db snr (a-weighted) input pga via lomix or romix to lout or rout, r l =16 , avdd=hpvdd= 2.7v 100 db thd (p o =20mw) -74 db thd+n (p o =20mw) -72 db thd (p o =5mw) -72 db thd+n (p o =5mw) -70 db f6 snr (a-weighted) line input to headphones via lomix and romix, r l =16 , avdd=hpvdd= 3.3v 104 db thd (p o =20mw) -77 db thd+n (p o =20mw) -75 db thd (p o =5mw) -73 db thd+n (p o =5mw) -71 db avdd psrr (217hz) 70 db hpvdd psrr (217hz) 85 db crosstalk (l/r) -95 db snr (a-weighted) line input to headphones via lomix and romix, r l =16 , avdd=hpvdd= 2.7v 102 db thd (p o =20mw) -74 db thd+n (p o =20mw) -72 db thd (p o =5mw) -72 db thd+n (p o =5mw) -70 db
wm8991 production data w pd, december 2008, rev 4.0 20 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit multi-path channel separation g1 headset voice call: dac/headset to tx voice separation 1khz 0dbfs dac playback to lout and rout; quiescent input on lin12 or rin12 (gain=+12db), differential output to lop/lon or rop/ron; measure crosstalk at lop/lon or rop/ron output 85 db g2 headset voice call: dac/speaker to tx voice separation 1khz 0dbfs dac playback to speaker, 1w output; quiescent input on lin12 or rin12 (gain=+12db), differential output to lop/lon or rop/ron; measure crosstalk at lop/lon or rop/ron output -1 100 db g3 pcm voice call: rx voice to tx voice separation fs=8khz for adc and dac, dac_sb_filt=1; -5dbfs differential mono output from dacs to out3/out4; quiescent input on input pga (gain=+12db) to adc via inmixl or inmixr; measure crosstalk at adc output 90 db g4 speakerphone pcm voice call: dac/speaker to adc separation fs=8khz for adc and dac, dac_sb_filt=1; 0dbfs dac output to speaker (1w output); adc record from input pga (gain=+30db); measure crosstalk on adc output 85 db g5 ear speaker voice call: tx voice and rx voice separation 1khz full scale differential input on rxp/rxn, output to out3/out4; quiescent input on lin12 or rin12 (gain=+12db), differential output to lop/lon or rop/ron; measure crosstalk at lop/lon or rop/ron output 70 db
production data wm8991 w pd, december 2008, rev 4.0 21 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit g6 headset voice call: tx voice and rx voice separation 1khz full scale differential input on rxp/rxn via rxvoice to lomix and romix, output to lout and rout; quiescent input on lin12 or rin12 (gain=+12db), differential output to lop/lon or rop/ron; measure crosstalk at lop/lon or rop/ron output - + +12db lin12 or rin12 (single-ended or differential mode) 0db lopmix or ropmix 0db load + 0db + 0db lomix romix full scale input c r o s s t a l k quiescent input rxvoice - + lin1 or rin1 lin2 or rin2 rxn rxp lout rout lop or rop lon or ron 75 db g7 stereo line record and playback: dac/headset to adc separation -5dbfs input to dacs, playback to lout and rout1; adc record from line input; measure crosstalk on adc output -5dbfs, 1khz -5dbfs, 1khz romix + dacr loutvol 0db dacl + lomix routvol 0db + inmixl or inmixr adcl or adcr crosstalk quiescent input lout rout lin2, lin4, rin2 or rin4 90 db
wm8991 production data w pd, december 2008, rev 4.0 22 test conditions dcvdd = 1.8v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, spkvdd = 5v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter test conditions min typ max unit analogue reference levels h1 vmid midrail reference voltage -3% avdd/2 +3% v microphone bias h2 bias voltage 3ma load current m1bsel=0 / m2bsel=0 -5% 0.9 avdd +5% v 3ma load current m1bsel=1 / m2bsel=1 -5% 0.65 avdd +5% v h3 bias current source 3 ma h4 output noise density 1khz to 20khz 100 nv/ hz h5 avdd psrr (217hz) 100mv pk-pk @217hz on avdd 45 db digital input / output h6 input high level 0.7 dbvdd v h7 input low level 0.3 dbvdd v note that digital input pins should not be left unconnected / floating. internal pull-up/pull-down resistors may be enabled on gpio1-6 if required. h8 output high level i ol =1ma 0.9 dbvdd v h9 output low level i oh =-1ma 0.1 dbvdd v h10 input capacitance 10 pf h11 input leakage -0.9 0.9 ua pll h12 input frequency prescale = 0b 7.7 18 mhz prescale = 1b 14.4 36 mhz h13 lock time 200 us gpio h14 clock output duty cycle (integer opclkdiv) sysclk=mclk; opclkdiv=0000 35 65 % sysclk=mclk; opclkdiv=1000 45 55 % sysclk=pll output; opclkdiv=0000 45 55 % sysclk=pll output; opclkdiv=1000 45 55 % h15 clock output duty cycle (non-integer opclkdiv) sysclk=mclk; opclkdiv=0100 33 66 % sysclk=pll output; opclkdiv=0100 33 66 % h16 interrupt response time for accessory / button detect input de-bounced 2 21 / f sysclk 2 22 / f sysclk s input de-bounced toclksel=1 2 19 / f sysclk 2 20 / f sysclk s input not de-bounced 0 s
production data wm8991 w pd, december 2008, rev 4.0 23 terminology 1. signal-to-noise ratio (db) ? snr is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. 2. total harmonic distortion (db) ? thd is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal. 3. total harmonic distortion plus noise (db) ? thd+n is the level of the rms value of the sum of harmonic distortion products plus noise in the specified bandwidth relative to the amplitude of the measured output signal. 4. crosstalk (l/r) (db) ? left-to-right and right-to-left channel crosstalk is the measured signal level in the idle channel at the test signal frequency relative to the signal level at the output of the active channel. the active channel is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the associated idle channel. for example, measured signal level on the output of the idle right channel (rin2 to adcr) with a full scale signal level at the output of the active left channel (lin1 to adcl). 5. multi-path channel separation (db) ? is the measured signal level in the idle path at the test signal frequency relative to the signal level at the output of the active path. the active path is configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. 6. all performance measurements carried out with 20khz low pass filter, and where noted an a-weighted filter. failure to use such a filter will result in higher thd and lower snr readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 7. mute attenuation ? this is a measure of the difference in level between the full scale output signal and the output with mute applied.
wm8991 production data w pd, december 2008, rev 4.0 24 typical power consumption control register other settings avdd hpvdd spkvdd dbvdd dcvdd iavdd ihpvdd ispkvdd idbvdd idcvdd total power mode vsel (v) (v) (v) (v) (v) (ma) (ma) (ma) (ma) (ma) (mw) off 01 no clocks 2.7 2.7 3.3 1.8 1.8 0.028 0.000 0.000 0.000 0.000 0.074 (default state at power-up) 11 3.0 3.0 3.6 2.5 2.5 0.029 0.000 0.000 0.000 0.000 0.086 11 3.3 3.3 4.2 3.3 3.3 0.030 0.000 0.000 0.000 0.000 0.099 11 3.6 3.6 5.0 3.6 3.6 0.031 0.000 0.000 0.000 0.000 0.114 off 01 no clocks 2.7 2.7 3.3 1.8 1.8 0.008 0.000 0.000 0.000 0.000 0.019 (thermal sensor disabled) 11 3.0 3.0 3.6 2.5 2.5 0.008 0.000 0.000 0.000 0.000 0.024 11 3.3 3.3 4.2 3.3 3.3 0.009 0.000 0.000 0.000 0.000 0.028 11 3.6 3.6 5.0 3.6 3.6 0.009 0.000 0.000 0.000 0.000 0.035 sleep 01 with clocks 2.7 2.7 3.3 1.8 1.8 0.087 0.000 0.000 0.004 0.459 1.067 (vmid enabled, thermal sensor anabled) 11 3.0 3.0 3.6 2.5 2.5 0.096 0.000 0.000 0.008 0.694 2.043 11 3.3 3.3 4.2 3.3 3.3 0.106 0.000 0.000 0.014 1.025 3.779 11 3.6 3.6 5.0 3.6 3.6 0.117 0.000 0.000 0.017 1.162 4.667 stereo line record 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 5.272 0.000 0.000 0.023 2.285 18.388 (l/rin2 to inmixl/r bypassing pga) 11 3.0 3.0 3.6 2.5 2.5 5.603 0.000 0.000 0.039 3.317 25.198 11 3.3 3.3 4.2 3.3 3.3 5.927 0.000 0.000 0.060 4.728 35.357 11 3.6 3.6 5.0 3.6 3.6 6.261 0.000 0.000 0.063 5.295 41.830 stereo line record 01 fs=8khz 2.7 2.7 3.3 1.8 1.8 5.125 0.000 0.000 0.017 0.758 15.232 (l/rin2 to inmixl/r bypassing pga) 11 3.0 3.0 3.6 2.5 2.5 5.434 0.000 0.000 0.027 1.123 19.176 11 3.3 3.3 4.2 3.3 3.3 5.738 0.000 0.000 0.061 1.634 24.527 11 3.6 3.6 5.0 3.6 3.6 6.053 0.000 0.000 0.062 1.841 28.642 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.950 0.705 0.000 0.003 2.147 13.739 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.315 0.558 0.000 0.007 3.180 19.586 16ohm load 11 3.3 3.3 4.2 3.3 3.3 3.684 0.640 0.000 0.013 4.544 29.307 11 3.6 3.6 5.0 3.6 3.6 4.055 0.726 0.000 0.016 5.092 35.600 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.951 1.430 0.000 0.004 2.298 15.971 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.315 1.367 0.000 0.007 3.380 22.513 -20dbv pink noise into 16ohm load 11 3.3 3.3 4.2 3.3 3.3 3.683 1.544 0.000 0.013 4.817 33.189 11 3.6 3.6 5.0 3.6 3.6 4.055 1.742 0.000 0.016 5.404 40.381 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.950 0.828 0.000 0.004 2.263 14.279 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.315 0.743 0.000 0.007 3.362 20.596 -30dbv pink noise into 16ohm load 11 3.3 3.3 4.2 3.3 3.3 3.684 0.835 0.000 0.013 4.762 30.671 11 3.6 3.6 5.0 3.6 3.6 4.056 0.937 0.000 0.016 5.344 37.270 playback to ac coupled headphones 01 fs=44.1khz 2. 7 2.7 3.3 1.8 1.8 2.950 2.563 0.000 0.004 2.251 18.943 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.315 2.476 0.000 0.007 3.323 25.698 0.1mw/channel into 16ohm load 11 3.3 3.3 4.2 3.3 3.3 3.683 2.508 0.000 0.014 4.736 36.103 11 3.6 3.6 5.0 3.6 3.6 4.055 2.556 0.000 0.016 5.304 42.951 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.952 15.767 0.000 0.004 2.256 54.608 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.316 15.789 0.000 0.007 3.343 65.690 5mw/channel into 16ohm load 11 3.3 3.3 4.2 3.3 3.3 3.683 15.675 0.000 0.013 4.762 79.640 11 3.6 3.6 5.0 3.6 3.6 4.055 15.836 0.000 0.016 5.329 90.850 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.951 0.699 0.000 0.004 2.147 13.725 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.317 0.550 0.000 0.007 3.179 19.565 32ohm load 11 3.3 3.3 4.2 3.3 3.3 3.684 0.629 0.000 0.013 4.543 29.268 11 3.6 3.6 5.0 3.6 3.6 4.055 0.711 0.000 0.016 5.089 35.536 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.951 1.019 0.000 0.004 2.302 14.868 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.315 0.915 0.000 0.007 3.359 21.105 -20dbv pink noise into 32ohm load 11 3.3 3.3 4.2 3.3 3.3 3.684 1.045 0.000 0.014 4.806 31.509 11 3.6 3.6 5.0 3.6 3.6 4.056 1.180 0.000 0.016 5.367 38.228 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.950 0.748 0.000 0.004 2.265 14.067 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.315 0.624 0.000 0.007 3.337 20.177 -30dbv pink noise into 32ohm load 11 3.3 3.3 4.2 3.3 3.3 3.683 0.704 0.000 0.013 4.786 30.314 11 3.6 3.6 5.0 3.6 3.6 4.055 0.789 0.000 0.016 5.359 36.789 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.950 1.950 0.000 0.004 2.253 17.291 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.315 1.868 0.000 0.007 3.327 23.883 0.1mw/channel into 32ohm load 11 3.3 3.3 4.2 3.3 3.3 3.683 1.905 0.000 0.014 4.741 34.129 11 3.6 3.6 5.0 3.6 3.6 4.055 1.950 0.000 0.016 5.312 40.799 playback to ac coupled headphones 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 2.955 11.421 0.000 0.004 2.267 42.901 (dac to l/rout) 11 3.0 3.0 3.6 2.5 2.5 3.319 11.362 0.000 0.007 3.351 52.438 5mw/channel into 32ohm load 11 3.3 3.3 4.2 3.3 3.3 3.686 11.349 0.000 0.014 4.777 65.423 11 3.6 3.6 5.0 3.6 3.6 4.057 11.406 0.000 0.016 5.342 74.956 playback to line-out 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 3.934 0.000 0.000 0.004 2.144 14.487 (dac to rop/ron) 11 3.0 3.0 3.6 2.5 2.5 4.184 0.000 0.000 0.007 3.179 20.517 11 3.3 3.3 4.2 3.3 3.3 4.672 0.000 0.000 0.013 4.541 30.446 11 3.6 3.6 5.0 3.6 3.6 5.166 0.000 0.000 0.016 5.089 36.976 playback to speaker class d 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 3.621 0.000 3.070 0.004 2.138 23.763 (dac to spk) 11 3.0 3.0 3.6 2.5 2.5 4.080 0.000 3.652 0.007 3.167 33.322 8ohm load 11 3.3 3.3 4.2 3.3 3.3 4.548 0.000 5.154 0.013 4.530 51.648 11 3.6 3.6 5.0 3.6 3.6 5.021 0.000 7.223 0.016 5.073 72.511 playback to speaker class ab 01 fs=44.1khz 2.7 2.7 3.3 1.8 1.8 3.087 0.000 2.823 0.004 2.125 21.482 (dac to spk) 11 3.0 3.0 3.6 2.5 2.5 3.470 0.000 3.307 0.007 3.146 30.198 8ohm load 11 3.3 3.3 4.2 3.3 3.3 3.856 0.000 4.061 0.013 4.496 44.662 11 3.6 3.6 5.0 3.6 3.6 4.246 0.000 5.057 0.016 5.042 58.780 fm radio to ac coupled headphones 01 2.7 2.7 3.3 1.8 1.8 0.442 0.697 0.000 0.000 0.000 3.074 (l/rin3 to l/rout bypass via lromix) 11 3.0 3.0 3.6 2.5 2.5 0.499 0.544 0.000 0.000 0.000 3.128 16ohm load 11 3.3 3.3 4.2 3.3 3.3 0.556 0.621 0.000 0.000 0.000 3.884 11 3.6 3.6 5.0 3.6 3.6 0.613 0.702 0.000 0.000 0.000 4.735 analogue voice call to handset ear speaker 01 2.7 2.7 3.3 1.8 1.8 2.307 0.796 0.000 0.000 0.000 8.377 (mic on lin12 to lop/lon) 11 3.0 3.0 3.6 2.5 2.5 2.374 0.615 0.000 0.000 0.000 8.966 (rxp/rxn to out3/4 via rxvioce & ainlmux) 11 3.3 3.3 4.2 3.3 3.3 2.660 0.703 0.000 0.000 0.000 11.097 11 3.6 3.6 5.0 3.6 3.6 2.953 0.794 0.000 0.000 0.000 13.490 pcm voice call 01 2.7 2.7 3.3 1.8 1.8 5.043 0.382 0.000 0.011 2.290 18.789 (mic on lin12 to ladc) 11 3.0 3.0 3.6 2.5 2.5 5.512 0.299 0.000 0.017 3.384 25.935 (-12db sidetone to ldac) 11 3.3 3.3 4.2 3.3 3.3 5.981 0.343 0.000 0.027 4.820 36.862 (ldac to out3, out4=mute) 11 3.6 3.6 5.0 3.6 3.6 6.457 0.389 0.000 0.032 5.386 44.150 notes: 1. power in the load is included. 2. all figures are quoted at t a = +25oc 3. all figures are quoted as quiescent current unless otherwise stated.
production data wm8991 w pd, december 2008, rev 4.0 25 speaker driver performance typical speaker driver thd+n performance is shown below for both class d and class ab modes. curves are shown for four typical spkvdd s upply voltage and gain combinations. load r l = 8 + 10 h, frequency = 1khz, +1db gain in active path. speaker class d into 8 + 10 h speaker class ab into 8 + 10 h speaker class d (8 +10 h) thd+n ratio v output power 0.001 0.01 0.1 1 10 0 0.25 0.5 0.75 1 1.25 1.5 output power (w) thd+n ratio (%) spkvdd=5.0v, ac=dc=1.52x spkvdd=4.2v, ac=dc=1.27x spkvdd=3.6v, ac=dc=1.00x spkvdd=3.3v, ac=dc=1.00x speaker class ab (8 +10 h) thd+n ratio v output power 0.001 0.01 0.1 1 10 0 0.25 0.5 0.75 1 1.25 1.5 output power (w) thd+n ratio (%) spkvdd=5.0v, ac=dc=1.52x spkvdd=4.2v, ac=dc=1.27x spkvdd=3.6v, ac=dc=1.00x spkvdd=3.3v, ac=dc=1.00x headphone driver performance typical thd+n performance of the headphone drivers is shown below (ac coupled to lout/rout). curves are shown for four hpvdd/avdd supply voltages. load r l = 16 and 32 , frequency = 1khz, +1db gain in active path. ac coupled headphone into 16 ac coupled headphone into 32 ac coupled headphone (16ohm) thd+n ratio v output power 0.01 0.1 1 10 0 1020304050607080 output power (mw) thd+n ratio (%) hpvdd=avdd=3.6v hpvdd=avdd=3.3v hpvdd=avdd=3.0v hpvdd=avdd=2.7v ac coupled headphone (32ohm) thd+n ratio v output power 0.01 0.1 1 10 0 1020304050607080 output power (mw) thd+n ratio (%) hpvdd=avdd=3.6v hpvdd=avdd=3.3v hpvdd=avdd=3.0v hpvdd=avdd=2.7v
wm8991 production data w pd, december 2008, rev 4.0 26 psrr performance spkvdd ? lin2 to speaker avdd ? lin2 to speaker psrr - spkvdd lin2 to spk class ab/d 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) lin2-spk (class d) - 5v spkvdd lin2-spk (class ab) - 5v spkvdd psrr - avdd lin2 to spk class ab/d 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) lin2-spk (class d 5v spkvdd) - 3.3v avdd lin2-spk (class ab 5v spkvdd) - 3.3v avdd spkvdd ? dac to speaker avdd ? dac to speaker psrr - spkvdd dac to spk class ab/d 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) dacl-spk (class d) - 5v spkvdd dacl-spk (class ab) - 5v spkvdd psrr - avdd dac to spk class ab/d 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) dacl-spk (class d 5v spkvdd) - 3.3v avdd dacl-spk (class ab 5v spkvdd) - 3.3v avdd hpvdd ? dac to headphone avdd ? dac to headphone psrr - hpvdd dac to hea dphone 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) dac-omix-lout/rout - 3.3v hpvdd dac-omix-opga-differential hp - 3.3v hpvdd psrr - avdd dac to hea dphone 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) dac-omix-lout/rout - 3.3v avdd dac-omix-opga-differential hp - 3.3v avdd dcvdd ? dac to headphone avdd ? micbias psrr - dcvdd dac to headphone 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 frequency (khz) psrr (db) dac-omix-lout/rout - 3.3v dcvdd dac-omix-lout/rout - 2.0v dcvdd psrr - avdd micbias 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) micbias - mbsel = 0 micbias - mbsel = 1
production data wm8991 w pd, december 2008, rev 4.0 27 dcvdd ? line-in to adc avdd ? line-in to adc psrr - dcvdd line-in to adc 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) in2-inmix-adc - 3.3v dcvdd in2-inmix-adc - 2.0v dcvdd psrr - avdd line-in to adc 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) in2-inmix-adc - 3.3v avdd in1pga-inmix-adc - 3.3v avdd hpvdd ? in1 bypass avdd ? in1 bypass psrr - hpvdd in1 bypass 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) in1pga-omix-lout/rout - 3.3v hpvdd psrr - avdd in1 bypass 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) in1pga-omix-lout/rout - 3.3v avdd in1pga-linediff - 3.3v avdd hpvdd ? in3 bypass avdd ? in3 bypass psrr - hpvdd in3 bypass 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) in3-omix-lout/rout - 3.3v hpvdd in3-omix-opga-out3/out4 - 3.3v hpvdd in3-omix-opga-differential hp - 3.3v hpvdd psrr - avdd in3 bypass 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 frequency (khz) psrr (db) in3-omix-lout/rout - 3.3v avdd in3-omix-opga -out3/ out4 - 3.3v av dd in3-omix-opga-differential hp - 3.3v avdd hpvdd ? in4 bypass avdd ? in4 bypass psrr - hpvdd in4 bypass 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 frequency (khz) psrr (db) rxvoice-omix-lout - 3.3v hpvdd in4-out3/out4 (16ohm btl) - 3.3v hpvdd psrr - avdd in4 bypass 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 frequency (khz) psrr (db) rxvoice-omix-lout - 3.3v avdd in4-out3/out4 (16ohm btl) - 3.3v avdd note: all figures based on 100mvp-p injected on the supply at the relevant test frequency.
wm8991 production data w pd, december 2008, rev 4.0 28 audio signal paths sdin sclk adcdat adclrc/gpio1 bclk dacdat daclrc mode csb/addr gpio5/dacdat2 gpio6/adclrcb dcvdd dbvdd dgnd spkgnd spkvdd hpvdd hpgnd gpio2/mclk2 gpio3/bclk2 gpio4/daclrc2 mclk avdd agnd vmid -1 -1
production data wm8991 w pd, december 2008, rev 4.0 29 signal timing requirements system clock timing figure 4 system clock timing requirements test conditions dcvdd=1.8v, dbvdd=avdd=3.3v, spkvdd=5v, dgnd=agnd=spkgnd=0v, t a = +25 o c parameter symbol conditions min typ max unit system clock timing information mclk or mclk2 cycle time t mclky 33.33 ns mclk or mclk2 duty cycle = t mclkh /t mclkl 60:40 40:60 mclk (or mclk2) t mclkl t mclkh t mclky
wm8991 production data w pd, december 2008, rev 4.0 30 audio interface timing ? master mode figure 5 digital audio data timing - master mode (see control interface) test conditions dcvdd=1.8v, dbvdd=avdd=3.3v, spkvdd=5v, dgnd=agnd=spkgnd=0v, t a =+25 o c, master mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data timing information adclrc/ daclrc (or daclrc2) propagation delay from bclk (or bclk2) falling edge t dl 20 ns adcdat propagation delay from bclk falling edge t dda 20 ns dacdat (or dacdat2) setup time to bclk rising edge t dst 20 ns dacdat (or dacdat2) hold time from bclk rising edge t dht 10 ns adclrc to adclrcb delay t dlrcb 10 ns
production data wm8991 w pd, december 2008, rev 4.0 31 audio interface timing ? slave mode figure 6 digital audio data timing ? slave mode test conditions dcvdd=1.8v, dbvdd=avdd=3.3, spkvdd=5v, dgnd=agnd=spkgnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data timing information bclk (or bclk2) cycle time t bcy 50 ns bclk (or bclk2) pulse width high t bch 20 ns bclk (or bclk2) pulse width low t bcl 20 ns adclrc/ daclrc (or daclrc2) set-up time to bclk (or bclk2) rising edge t lrsu 20 ns adclrc/ daclrc (or daclrc2) hold time from bclk (or bclk2) rising edge t lrh 10 ns dacdat (or dacdat2) hold time from bclk (or bclk2) rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 20 ns dacdat (or dacdat2) set-up time to bclk (or bclk2) rising edge t ds 20 ns adclrc to adclrcb delay t dlrcb 20 ns note: bclk (or bclk2) period should always be greater than or equal to mclk (or mclk2) period.
wm8991 production data w pd, december 2008, rev 4.0 32 audio interface timing ? tdm mode in tdm mode, it is important that two adc devices to not attempt to drive the adcdat pin simultaneously. the timing of the wm8991 adcdat tri-stating at the start and end of the data transmission is described in figure 7 and the table below. figure 7 digital audio data timing - tdm mode test conditions dbvdd=avdd=3.3v, spkvdd=5v, dgnd=agnd=spkgnd=0v, t a =+25 o c, master mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter conditions min typ max unit audio data timing information adcdat setup time from bclk falling edge dcvdd = dbvdd = 3.6v 5 ns dcvdd = dbvdd = 1.71v 15 ns adcdat release time from bclk falling edge dcvdd = dbvdd = 3.6v 5 ns dcvdd = dbvdd = 1.71v 15 ns
production data wm8991 w pd, december 2008, rev 4.0 33 control interface timing ? 2-wire mode 2-wire mode is selected by connecting the mode pin low. sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 8 control interface timing ? 2-wire serial control mode test conditions dcvdd=1.8v, dbvdd=avdd=hpvdd=3.3, spkvdd=5v, dgnd=agnd=hpgnd=spkgnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
wm8991 production data w pd, december 2008, rev 4.0 34 control interface timing ? 3-wire mode 3-wire mode is selected by connecting the mode pin high. figure 9 control interface timing ? 3-wire serial control mode (write cycle) csb sclk sdout t dl lsb figure 10 control interface timing - 3-wire serial control mode (read cycle) test conditions dcvdd=1.8v, dbvdd=avdd=hpvdd=3.3v, spkvdd=5v, dgnd=agnd=hpgnd=spkgnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information csb falling edge to sclk rising edge t csu 40 ns sclk falling edge to csb rising edge t cho 40 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sdin to sclk hold time t dho 10 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk falling edge to sdout transition t dl 40 ns
production data wm8991 w pd, december 2008, rev 4.0 35 control interface timing ? 4-wire mode 4-wire mode supports readback via sdout which is available as a gpio pin function. csb sclk sdin t dho t dsu t scy t cho lsb t csu figure 11 control interface timing ? 4-wire serial control mode (write cycle) csb sclk sdout t dl lsb figure 12 control interface timing ? 4-wire serial control mode (read cycle) test conditions dcvdd=1.8v, dbvdd=avdd=hpvdd=3.3v, spkvdd=5v, dgnd=agnd=hpgnd=spkgnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb falling edge t csu 40 ns sclk falling edge to csb rising edge t cho 40 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sdin to sclk hold time t dho 10 ns sdout propagation delay from sclk rising edge t dl 10 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk falling edge to sdout transition t dl 40 ns
wm8991 production data w pd, december 2008, rev 4.0 36 internal power on reset circuit figure 13 internal power on reset circuit schematic the wm8991 includes an internal power-on-reset circuit, as shown in figure 13, which is used to reset the digital logic into a default state after power up. the por circuit is powered from avdd and monitors dcvdd. it asserts porb low if avdd or dcvdd is below a minimum threshold. figure 14 typical power up sequence where avdd is powered before dcvdd figure 14 shows a typical power-up sequence where avdd comes up first. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. now avdd is at full supply level. next dcvdd rises to v pord_on and porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where avdd falls first, porb is asserted low whenever avdd drops below the minimum threshold v pora_off .
production data wm8991 w pd, december 2008, rev 4.0 37 figure 15 typical power up sequence where dcvdd is powered before avdd figure 15 shows a typical power-up sequence where dcvdd comes up first. first it is assumed that dcvdd is already up to specified operating voltage. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when avdd rises to v pora_on , porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where dcvdd falls first, porb is asserted low whenever dcvdd drops below the minimum threshold v pord_off . symbol min typ max unit vpora 0.6 v vpora_on 1.52 v vpora_off 1.5 v vpord_on 0.92 v vpord_off 0.9 v table 1 typical por operation (typical values, not tested) notes: 1. if avdd and dcvdd suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below v pora_off or v pord_off ) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. 2. the chip will enter reset at power down when avdd or dcvdd falls below v pora_off or v pord_off . this may be important if the supply is turned on and off frequently by a power management system. 3. the minimum t por period is maintained even if dcvdd and avdd have zero rise time. this specification is guaranteed by design rather than test.
wm8991 production data w pd, december 2008, rev 4.0 38 device description introduction the wm8991 is a low power, high quality audio codec designed to interface with a wide range of processors and analogue components. a high level of mixed-signal integration in a small 5x5mm footprint makes it ideal for portable applications such as mobile phones. eight highly flexible analogue inputs allow interfacing to up to four microphone inputs plus multiple stereo or mono line inputs (single-ended or differential). connections to an external voice codec, fm radio, melody ic, line input, handset mic and headset mic are all fully supported. signal routing to the output mixers and within the codec has been designed for maximum flexibility to support a wide variety of usage modes. ten analogue output drivers are integrated, including a high power, high quality speaker driver, capable of providing 1w in class d mode or in class ab mode into 8 btl. four headphone drivers are provided, supporting ear speakers and stereo headsets. fully differential headphone drive is supported for excellent crosstalk performance and removing the need for large and expensive headphone capacitors. four line outputs are available for tx voice output to a voice codec, interfacing to an additional speaker driver and single-ended or fully differential line output. all outputs have integrated pop and click suppression. the speaker supply has been designed with low leakage and high psrr, to support direct connection to a lithium battery. in addition to the speaker pga, six ac and dc gain settings allow output signal level to be maximised for many commonly-used spkvdd/avdd combinations. internal signal routing and amplifier configurations have been optimised to provide the lowest possible power consumption for a number of common usage scenarios such as voice calls and music playback. the stereo adcs and dacs are of hi-fi quality using a 24-bit, low-order oversampling architecture to deliver optimum performance. a flexible clocking arrangement supports mixed adc and dac sample rates, while an integrated ultra-low power pll provides additional flexibility. a high pass filter is available in the adc path for removing dc offsets and suppressing low frequency noise such as mechanical vibration and wind noise. a digital mixing path from the adc to the dac provides a sidetone of enhanced quality during voice calls. dac soft mute and un-mute is available for pop-free music playback. the wm8991 has a highly flexible digital audio interface, supporting a number of protocols, including i 2 s, dsp, msb-first left/right justified, and can operate in master or slave modes. pcm operation is supported in the dsp mode. a-law and -law companding are also supported. time division multiplexing (tdm) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. alternative dac interface pins are provided to allow connection to an additional processor. the sysclk (system clock) provides clocking for the adcs, dacs, dsp core, class d outputs and the digital audio interface. sysclk can be derived directly from the mclk pin or via an integrated pll, providing flexibility to support a wide range of clocking schemes. all mclk frequencies typically used in portable systems are supported for sample rates between 8khz and 48khz. a flexible switching clock for the class d speaker drivers (synchronous with the audio dsp clocks for best performance) is also derived from sysclk. an additional master clock input pin is provided, to support operation on an alternative clock domain, selectable via a de-glitch circuit. to allow full software control over all its features, the wm8991 uses a standard 2-wire or 3/4-wire control interface with readback of key registers supported. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. unused circuitry can be disabled via software to save power, while low leakage currents extend standby and off time in portable battery-powered applications. the device address can be selected using the csb/addr pin. versatile gpio functionality is provided, with support for up to seven button/accessory detect inputs with interrupt and status readback and flexible de-bouncing options, clock output, alternative mclk input, adclrc inversion for simultaneous streaming of adc data to two separate processors and logic '1' / logic '0' for control of additional external circuitry.
production data wm8991 w pd, december 2008, rev 4.0 39 input signal path the wm8991 has eight highly flexible analogue input channels, configurable in many combinations of the following: 1. up to four pseudo-differential or single-ended microphone inputs 2. up to eight mono line inputs or 4 stereo line inputs 3. mono input from external voice codec 4. two fully balanced differential inputs these inputs may be mixed together or independently routed to different combinations of output drivers. an internal record path is provided at the input mixers to allow dac output to be mixed with the input signal path (e.g. for karaoke or voice call recording). the wm8991 input signal paths and control registers are illustrated in figure 16. figure 16 control registers for input signal path
wm8991 production data w pd, december 2008, rev 4.0 40 microphone inputs up to four microphones can be connected to the wm8991, either in single-ended or pseudo- differential mode. a low noise microphone bias is fully integrated to reduce the need for external components. in single-ended microphone input configuration, the microphone signal is connected to the inverting input of the pga (lin1, lin3, rin1 or rin3). the non-inverting input of the pgas should be internally connected to vmid in this configuration. this is enabled via the input pga configuration register settings. in this configuration, lin2, lin4, rin2 or rin4 may be free to be used as line inputs or adc bypass inputs. in pseudo-differential microphone input configuration, the non-inverted microphone signal is connected to the non-inverting input of the pga (lin2, lin4, rin2 or rin4) and the inverted (or noisy ground) signal is connected to the inverting input (lin1, lin3, rin1 or rin3). any pga input pin that is used in either microphone configuration should not be enabled as a line input path at the same time. the gain of the input pgas is controlled via register settings. note that the input impedance of lin1, lin3, rin1 and rin3 changes with the input pga gain setting, as described under ?electrical characteristics?. (note this does not apply to input paths which bypass the input pga.) the input impedance of lin2, lin4, rin2 and rin4 does not change with input pga gain. the inverting and non-inverting inputs are therefore not matched and the differential configuration is not fully differential. figure 17 single-ended microphone input figure 18 differential microphone input
production data wm8991 w pd, december 2008, rev 4.0 41 line inputs all eight analogue input pins may be configured as line inputs. various signal paths exist to provide flexibility, high performance and low power consumption for different usage modes. lin1 and rin1 can operate as line inputs to the input pgas lin12 and rin12 to provide high gain if required for small input signals. lin2 and rin2 can operate as line inputs directly to the input mixers or to the speaker output mixer. direct routing to the speaker output minimises power consumption by reducing the number of active amplifiers in the signal path. lin3 and rin3 can operate as line inputs to the input pgas or as a line input directly to either of the output mixers lomix and romix. lin1+lin3 and rin1+rin3 can also be used as fully balanced differential inputs via the input pgas to one of the input mixers. (note that these inputs have matched input impedances.) lin4/rxn and rin4/rxp can operate as line inputs directly to the outputs out3 and out4, providing an ultra-low power stereo or mono differential signal path (e.g. from an external voice codec) to an ear speaker. lin4/rxn and rin4/rxp can also operate as a mono differential input to the adc input signal path and output mixer stages. figure 19 lin1 or rin1 as line inputs figure 20 lin2 or rin2 as line inputs figure 21 lin3 or rin3 as line inputs figure 22 fully balanced differential input
wm8991 production data w pd, december 2008, rev 4.0 42 figure 23 lin4 and rin4 as rx voice inputs with direct low power path to ear speaker figure 24 lin4 or rin4 as line inputs
production data wm8991 w pd, december 2008, rev 4.0 43 input pga enable the input pgas are enabled using register bits lin12_ena, lin34_ena, rin12_ena and rin34_ena as described in table 2. register address bit label default description r2 (02h) 7 lin34_ena (rw) 0b lin34 input pga enable 0 = disabled 1 = enabled 6 lin12_ena (rw) 0b lin12 input pga enable 0 = disabled 1 = enabled 5 rin34_ena (rw) 0b rin34 input pga enable 0 = disabled 1 = enabled 4 rin12_ena (rw) 0b rin12 input pga enable 0 = disabled 1 = enabled table 2 input pga enable to enable the input pgas, the reference voltage vmid and the bias current must also be enabled. see ?power management? for definitions of the associated controls vmid_mode and vref_ena. microphone bias control the micbias output provides a low noise reference voltage suitable for biasing electret type microphones via an external resistor. refer to the applications information section for recommended external components. the micbias voltage can be enabled or disabled using the micbias_ena control bit and the voltage can be selected using the mbsel register bit as detailed in table 3. register address bit label default description r1 (01h) 4 micbias_ena (rw) 0b microphone bias 0 = off (high impedance output) 1 = on r58 (3ah) 0 mbsel 0b microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd table 3 microphone bias control note that the maximum source current capability for micbias is 3ma. the external biasing resistance must be large enough to limit the micbias current to 3ma. microphone current detect a micbias current detect function allows detection of accessories such as headset microphones. when the micbias load current exceeds one of two programmable thresholds, (e.g. short circuit current or normal operating current), an interrupt or gpio output can be generated. the current detection circuit is enabled by the mcd bit; the current thresholds are selected by the mcdthr and mcdscth register fields as described in table 49- see ?general purpose input/output? for a full description of these fields.
wm8991 production data w pd, december 2008, rev 4.0 44 input pga configuration each of the four input pgas can be configured in single-ended or pseudo-differential mode. single-ended microphone operation of an input pga is selected by connecting the input source to the inverting pga input. the non-inverting pga input must be connected to vmid by setting the appropriate register bits. for pseudo-differential microphone operation, the inverting and non-inverting pga inputs are both connected to the input source and not to vmid. for any line input or other connection not using the input pga, the appropriate pga input should be disconnected from the external pin and connected to vmid. register bits lmn1, lmp2, lmn3, lmp4, rmn1, rmp2, rmn3 and rmp4 control connection of the pga inputs to the device pins as shown in table 4. the maximum available attenuation on any of these input paths is achieved using these bits to disable the input path to the applicable pga. when not enabled as analogue inputs or as general purpose inputs, the input pins can be biased to vref via a 1k resistor by setting the bufioen bit. see ?pop suppression control? for details. register address bit label default description r40 (28h) 7 lmp4 0b lin34 pga non-inverting input select 0 = lin4 not connected to pga 1 = lin4 connected to pga 6 lmn3 0b lin34 pga inverting input select 0 = lin3 not connected to pga 1 = lin3 connected to pga 5 lmp2 0b lin12 pga non-inverting input select 0 = lin2 not connected to pga 1 = lin2 connected to pga 4 lmn1 0b lin12 pga inverting input select 0 = lin1 not connected to pga 1 = lin1 connected to pga 3 rmp4 0b rin34 pga non-inverting input select 0 = rin4 not connected to pga 1 = rin4 connected to pga 2 rmn3 0b rin34 pga inverting input select 0 = rin3 not connected to pga 1 = rin3 connected to pga 1 rmp2 0b rin12 pga non-inverting input select 0 = rin2 not connected to pga 1 = rin2 connected to pga 0 rmn1 0b rin12 pga inverting input select 0 = rin1 not connected to pga 1 = rin1 connected to pga table 4 input pga configuration
production data wm8991 w pd, december 2008, rev 4.0 45 input pga volume control each of the four input pgas has an independently controlled gain range of -16.5db to +30db in 1.5db steps. the gains on the inverting and non-inverting inputs to the pgas are always equal. each input pga can be independently muted using the pga mute bits as described in table 5, with specified mute attenuation achieved by simultaneously disconnecting the corresponding inputs described in table 4. to prevent "zipper noise", a zero-cross function is provided, so that when enabled, volume updates will not take place until a zero-crossing is detected. in the event of a long period without zero- crossings, a timeout function is available. when this function is enabled (using the toclk_ena register bit), the volume will update after the timeout period if no earlier zero-cross has occurred. the timeout period is set by toclk_rate. see ?clocking and sample rates? for more information on these fields. the ipvu bit controls the loading of the input pga volume data. when ipvu is set to 0, the pga volume data will be loaded into the respective control register, but will not actually change the gain setting. the lin12, rin12, lin34, rin34 volume settings are all updated when a 1 is written to ipvu. this makes it possible to update the gain of all input paths simultaneously. the input pga volume control register fields are described in table 5 and table 6. register address bit label default description r24 (18h) 8 ipvu[0] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 li12mute 1b lin12 pga mute 0 = disable mute 1 = enable mute 6 li12zc 0b lin12 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 4:0 lin12vol [4:0] 01011b (0db) lin12 volume (see table 6 for volume range) r25 (19h) 8 ipvu[1] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 li34mute 1b lin34 pga mute 0 = disable mute 1 = enable mute 6 li34zc 0b lin34 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 4:0 lin34vol [4:0] 01011b (0db) lin34 volume (see table 6 for volume range) r26 (1ah) 8 ipvu[2] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 ri12mute 1b rin12 pga mute 0 = disable mute 1 = enable mute 6 ri12zc 0b rin12 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only
wm8991 production data w pd, december 2008, rev 4.0 46 register address bit label default description 4:0 rin12vol [4:0] 01011b (0db) rin12 volume (see table 6 for volume range) r27 (1bh) 8 ipvu[3] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 ri34mute 1b rin34 pga mute 0 = disable mute 1 = enable mute 6 ri34zc 0b rin34 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 4:0 rin34vol [4:0] 01011b (0db) rin34 volume (see table 6 for volume range) table 5 input pga volume control
production data wm8991 w pd, december 2008, rev 4.0 47 lin12vol[4:0], lin34vol[4:0], rin12vol[4:0], rin34vol[4:0] volume (db) 00000 -16.5 00001 -15.0 00010 -13.5 00011 -12.0 00100 -10.5 00101 -9.0 00110 -7.5 00111 -6.0 01000 -4.5 01001 -3.0 01010 -1.5 01011 0 01100 +1.5 01101 +3.0 01110 +4.5 01111 +6.0 10000 +7.5 10001 +9.0 10010 +10.5 10011 +12.0 10100 +13.5 10101 +15.0 10110 +16.5 10111 +18.0 11000 +19.5 11001 +21.0 11010 +22.5 11011 +24.0 11100 +25.5 11101 +27.0 11110 +28.5 11111 +30.0 table 6 input pga volume range
wm8991 production data w pd, december 2008, rev 4.0 48 input mixer enable the wm8991 has two analogue input mixers which allow the input pgas and line inputs to be combined in a number of ways and output to the adcs or to the output mixers via bypass paths. the input mixers inmixl and inmixr are enabled by the ainl_ena and ainr_ena register bits, as described in table 7. these control bits also enable the input multiplexers and differential input drivers, described in the following section. register address bit label default description r2 (02h) 9 ainl_ena (rw) 0b left input path enable (enables ainlmux, inmixl, diffinl and rxvoice input to ainlmux) 0 = input path disabled 1 = input path enabled 8 ainr_ena (rw) 0b right input path enable (enables ainrmux, inmixr, diffinr and rxvoice input to ainrmux) 0 = input path disabled 1 = input path enabled table 7 input mixer enable input mixer configuration the left and right channel input multiplexers ainlmux and ainrmux select one of three input sources for the left and right channels independently. the three input sources are as follows: 1. inmixl or inmixr output (a combination of input pgas, line inputs and the internal record path). 2. rxvoice (a differential to single-ended conversion of rxp and rxn inputs). 3. diffinl or diffinr output (a differential to single-ended conversion of two input pgas). the input source for the multiplexers is controlled by register bits ainlmode and ainrmode as described in table 8. register address bit label default description r39 (27h) 3:2 ainlmode [1:0] 00b ainlmux input source 00 = inmixl (left input mixer) 01 = rxvoice (rxp - rxn) 10 = diffinl (lin12 pga - lin34 pga) 11 = (reserved) 1:0 ainrmode [1:0] 00b ainrmux input source 00 = inmixr (right input mixer) 01 = rxvoice (rxp - rxn) 10 = diffinr (rin12 pga - rin34 pga) 11 = (reserved) table 8 input mixer configuration the input mixer configuration is described for each of the three modes in the following sections. note that the left and right multiplexer (mode) settings can be set independently.
production data wm8991 w pd, december 2008, rev 4.0 49 in mixer mode (ainlmode=00, ainrmode=00), adjustable gain control is available on the input mixers inmixl and inmixr for all available input signals (pga outputs, line inputs and record paths). this configuration is illustrated in figure 25. the applicable register settings are shown in table 9. configuration register settings left channel mixer mode (inmixl to ainlmux) 1. select mixer mode ainlmode = 00 2. enable input paths as required (see table 5 and table 12 for full definitions of the applicable settings listed here) l12mnb, l12mnbst lin12vol, lin12mute l34mnb, l34mnbst lin34vol, lin34mute ldbvol li2bvol right channel mixer mode (inmixr to ainrmux) 1. select mixer mode ainrmode = 00 2. enable input paths as required (see table 5 and table 13 for full definitions of the applicable settings listed here) r12mnb, r12mnbst rin12vol, rin12mute r34mnb, r34mnbst rin34vol, rin34mute rdbvol ri2bvol table 9 mixer mode register settings figure 25 mixer mode signal paths
wm8991 production data w pd, december 2008, rev 4.0 50 in rx voice mode (ainlmode=01, ainrmode=01), adjustable gain control is available for the rxvoice output by use of the lr4bvol[2:0] and ll4bvol[2:0] register fields on the left channel and by rl4bvol[2:0] and rr4bvol[2:0] on the right channel. both volume fields for the desired channel(s) must be set to the same value for true differential input characteristics. this configuration is illustrated in figure 26. the applicable register settings are shown in table 10. configuration register settings left channel rx voice mode (rxvoice to ainlmux) 1. select rx voice mode ainlmode = 01 2. enable rx voice input as required important: these two register fields must be set to the same value. see table 12 for full definitions of these fields. ll4bvol lr4bvol right channel rx voice mode (rxvoice to ainrmux) 1. select rx voice mode ainrmode = 01 2. enable rx voice input as required important: these two register fields must be set to the same value. see table 13 for full definitions of these fields. rl4bvol rr4bvol table 10 rxvoice mode register settings figure 26 rxvoice mode signal paths
production data wm8991 w pd, december 2008, rev 4.0 51 in differential mode (ainlmode=10, ainrmode=10), no additional volume control is available in the input signal path, but the input pga volume control can be used to adjust the signal level as with other modes. both pgas on the desired channel(s) must be enabled, and the pga volumes of each set to the same value for true differential input characteristics. the pga output (lin12 or rin12) to mixer (inmixl or inmixr) path must also be enabled on the desired channel(s) by use of register bit l12mnb or r12mnb. this configuration is illustrated in figure 27. the applicable register settings are shown in table 11. configuration register settings left channel differential mode (diffinl to ainlmux) 1. select differential mode ainlmode = 10 2. enable lin12 input path l12mnb = 1 3. set channel volume as required. important: the lin12 and lin34 volume and mute settings must be set to the same value. see table 5 for full definitions of these fields. lin12vol, lin12mute lin34vol, lin34mute right channel differential mode (diffinr to ainrmux) 1. select differential mode ainrmode = 10 2. enable rin12 input path r12mnb = 1 3. set channel volume as required. important: the rin12 and rin34 volume and mute settings must be set to the same value. see table 5 for full definitions of these fields. rin12vol, rin12mute rin34vol, rin34mute table 11 differential mode register settings figure 27 differential mode signal paths input mixer volume control the input mixer volume controls are described in table 12 for the left channel and table 13 for the right channel. the input pga levels may be set to mute, 0db or 30db boost. the other gain controls provide adjustment from -12db to +6db in 3db steps. to prevent pop noise it is recommended that gain and mute controls for the input mixers are not modified while the signal paths are active. if volume control is required on the input signal path it is recommended that the input pga volume controls or the adc volume controls are used instead of the input mixer gain registers.
wm8991 production data w pd, december 2008, rev 4.0 52 register address bit label default description r41 (29h) 8 l34mnb 0b lin34 pga output to inmixl mute 0 = mute 1 = un-mute 7 l34mnbst 0b lin34 pga output to inmixl gain 0 = 0db 1 = +30db 5 l12mnb 0b lin12 pga output to inmixl mute 0 = mute 1 = un-mute 4 l12mnbst 0b lin12 pga output to inmixl gain 0 = 0db 1 = +30db 2:0 ldbvol [2:0] 000b (mute) lomix to inmixl gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r43 (2bh) 8:6 li2bvol [2:0] 000b (mute) lin2 pin to inmixl gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 5:3 lr4bvol [2:0] 000b (mute) rxvoice to ainlmux gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 2:0 ll4bvol [2:0] 000b (mute) rxvoice to inmixl gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db note - lr4bvol must be set to the same value as ll4bvol when ainlmode=01. table 12 left input mixer volume control
production data wm8991 w pd, december 2008, rev 4.0 53 register address bit label default description r42 (2a) 8 r34mnb 0b rin34 pga output to inmixr mute 0 = mute 1 = un-mute 7 r34mnbst 0b rin34 pga output to inmixr gain 0 = 0db 1 = +30db 5 r12mnb 0b rin12 pga output to inmixr mute 0 = mute 1 = un-mute 4 r12mnbst 0b rin12 pga output to inmixr gain 0 = 0db 1 = +30db 2:0 rdbvol [2:0] 000b (mute) romix to inmixr gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r44 (2ch) 8:6 ri2bvol [2:0] 000b (mute) rin2 pin to inmixr gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 5:3 rl4bvol [2:0] 000b (mute) rxvoice to ainrmux gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 2:0 rr4bvol [2:0] 000b (mute) rxvoice to inmixr gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db note - rl4bvol must be set to the same value as rr4bvol when ainrmode=01. table 13 right input mixer volume control
wm8991 production data w pd, december 2008, rev 4.0 54 analogue to digital converter (adc) the wm8991 uses stereo 24-bit, 64x oversampled sigma-delta adcs. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input level is proportional to avdd. see ?electrical characteristics? for further details. any input signal greater than full scale may overload the adc and cause distortion. the adcs are enabled by the adcl_ena and adcr_ena register bits. if both adcs are to be enabled, they should be enabled simultaneously, i.e. with the same register write. if there is a requirement to enable the adcs independently of one another and use them simultaneously, the adcl_adcr_link bit should be set. the ext_acc ess_ena bit must be set before writing to the adcl_adcr_link bit. register address bit label default description r2 (02h) 1 adcl_ena (rw) 0b left adc enable 0 = adc disabled 1 = adc enabled 0 adcr_ena (rw) 0b right adc enable 0 = adc disabled 1 = adc enabled r117 (75h) 1 ext_access_ena 0b extended register map access 0 = disabled 1 = enabled r122 (7ah) 15 adcl_adcr_link 0b 0 = adc sync disabled 1 = adc sync enabled table 14 adc enable control adc digital volume control the output of the adcs can be digitally amplified or attenuated over a range from -71.625db to +17.625db in 0.375db steps. the volume of each channel can be controlled separately. the gain for a given eight-bit code x is given by: 0.375 (x-192) db for 1 x 239; mute for x = 0 +17.625db for 239 x 255 the adc_vu bit controls the loading of digital volume control data. when adc_vu is set to 0, the adcl_vol or adcr_vol control data will be loaded into the respective control register, but will not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to adc_vu. this makes it possible to update the gain of both channels simultaneously. register address bit label default description r15 (0fh) 8 adc_vu n/a adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 7:0 adcl_vol [7:0] 1100_0000b (0db) left adc digital volume (see table 16 for volume range) r16 (10h) 8 adc_vu n/a adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 7:0 adcr_vol [7:0] 1100_0000b (0db) right adc digital volume (see table 16 for volume range) table 15 adc digital volume control
production data wm8991 w pd, december 2008, rev 4.0 55 adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.375 2h -71.250 42h -47.250 82h -23.250 c2h 0.750 3h -70.875 43h -46.875 83h -22.875 c3h 1.125 4h -70.500 44h -46.500 84h -22.500 c4h 1.500 5h -70.125 45h -46.125 85h -22.125 c5h 1.875 6h -69.750 46h -45.750 86h -21.750 c6h 2.250 7h -69.375 47h -45.375 87h -21.375 c7h 2.625 8h -69.000 48h -45.000 88h -21.000 c8h 3.000 9h -68.625 49h -44.625 89h -20.625 c9h 3.375 ah -68.250 4ah -44.250 8ah -20.250 cah 3.750 bh -67.875 4bh -43.875 8bh -19.875 cbh 4.125 ch -67.500 4ch -43.500 8ch -19.500 cch 4.500 dh -67.125 4dh -43.125 8dh -19.125 cdh 4.875 eh -66.750 4eh -42.750 8eh -18.750 ceh 5.250 fh -66.375 4fh -42.375 8fh -18.375 cfh 5.625 10h -66.000 50h -42.000 90h -18.000 d0h 6.000 11h -65.625 51h -41.625 91h -17.625 d1h 6.375 12h -65.250 52h -41.250 92h -17.250 d2h 6.750 13h -64.875 53h -40.875 93h -16.875 d3h 7.125 14h -64.500 54h -40.500 94h -16.500 d4h 7.500 15h -64.125 55h -40.125 95h -16.125 d5h 7.875 16h -63.750 56h -39.750 96h -15.750 d6h 8.250 17h -63.375 57h -39.375 97h -15.375 d7h 8.625 18h -63.000 58h -39.000 98h -15.000 d8h 9.000 19h -62.625 59h -38.625 99h -14.625 d9h 9.375 1ah -62.250 5ah -38.250 9ah -14.250 dah 9.750 1bh -61.875 5bh -37.875 9bh -13.875 dbh 10.125 1ch -61.500 5ch -37.500 9ch -13.500 dch 10.500 1dh -61.125 5dh -37.125 9dh -13.125 ddh 10.875 1eh -60.750 5eh -36.750 9eh -12.750 deh 11.250 1fh -60.375 5fh -36.375 9fh -12.375 dfh 11.625 20h -60.000 60h -36.000 a0h -12.000 e0h 12.000 21h -59.625 61h -35.625 a1h -11.625 e1h 12.375 22h -59.250 62h -35.250 a2h -11.250 e2h 12.750 23h -58.875 63h -34.875 a3h -10.875 e3h 13.125 24h -58.500 64h -34.500 a4h -10.500 e4h 13.500 25h -58.125 65h -34.125 a5h -10.125 e5h 13.875 26h -57.750 66h -33.750 a6h -9.750 e6h 14.250 27h -57.375 67h -33.375 a7h -9.375 e7h 14.625 28h -57.000 68h -33.000 a8h -9.000 e8h 15.000 29h -56.625 69h -32.625 a9h -8.625 e9h 15.375 2ah -56.250 6ah -32.250 aah -8.250 eah 15.750 2bh -55.875 6bh -31.875 abh -7.875 ebh 16.125 2ch -55.500 6ch -31.500 ach -7.500 ech 16.500 2dh -55.125 6dh -31.125 adh -7.125 edh 16.875 2eh -54.750 6eh -30.750 aeh -6.750 eeh 17.250 2fh -54.375 6fh -30.375 afh -6.375 efh 17.625 30h -54.000 70h -30.000 b0h -6.000 f0h 17.625 31h -53.625 71h -29.625 b1h -5.625 f1h 17.625 32h -53.250 72h -29.250 b2h -5.250 f2h 17.625 33h -52.875 73h -28.875 b3h -4.875 f3h 17.625 34h -52.500 74h -28.500 b4h -4.500 f4h 17.625 35h -52.125 75h -28.125 b5h -4.125 f5h 17.625 36h -51.750 76h -27.750 b6h -3.750 f6h 17.625 37h -51.375 77h -27.375 b7h -3.375 f7h 17.625 38h -51.000 78h -27.000 b8h -3.000 f8h 17.625 39h -50.625 79h -26.625 b9h -2.625 f9h 17.625 3ah -50.250 7ah -26.250 bah -2.250 fah 17.625 3bh -49.875 7bh -25.875 bbh -1.875 fbh 17.625 3ch -49.500 7ch -25.500 bch -1.500 fch 17.625 3dh -49.125 7dh -25.125 bdh -1.125 fdh 17.625 3eh -48.750 7eh -24.750 beh -0.750 feh 17.625 3fh -48.375 7fh -24.375 bfh -0.375 ffh 17.625 table 16 adc digital volume range
wm8991 production data w pd, december 2008, rev 4.0 56 high pass filter a digital high pass filter is applied by default to the adc path to remove dc offsets. this filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or mechanical vibration). this filter is controlled using the adc_hpf_ena and adc_hpf_cut register bits. in hi-fi mode the high pass filter is optimised for removing dc offsets without degrading the bass response and has a cut-off frequency of 3.7hz at fs=44.1khz. in voice mode the high pass filter is optimised for voice communication and it is recommended to program the cut-off frequency below 300hz (e.g. adc_hpf_cut=11 at fs=8khz or adc_hpf_cut=10 at fs=16khz). register address bit label defaul t description r14 (0eh) 8 adc_hpf_ena 1b adc digital high pass filter enable 0 = disabled 1 = enabled 6:5 adc_hpf_cut [1:0] 00b adc digital high pass filter cut-off frequency (fc) 00 = hi-fi mode (fc=4hz at fs=48khz) 01 = voice mode 1 (fc=127hz at fs=16khz) 10 = voice mode 2 (fc=130hz at fs=8khz) 11 = voice mode 3 (fc=267hz at fs=8khz) (note: fc scales with sample rate. see table 18 for cut-off frequencies at all supported sample rates) table 17 adc high pass filter control registers sample frequenc y (khz) cut-off frequency (hz) adc_hpf_cut =00 adc_hpf_cut =01 adc_hpf_cut =10 adc_hpf_cut =11 8.000 0.7 64 130 267 11.025 0.9 88 178 367 16.000 1.3 127 258 532 22.050 1.9 175 354 733 24.000 2.0 190 386 798 32.000 2.7 253 514 1063 44.100 3.7 348 707 1464 48.000 4.0 379 770 1594 table 18 adc high pass filter cut-off frequencies the high pass filter characteristics are shown in the "digital filter characteristics" section.
production data wm8991 w pd, december 2008, rev 4.0 57 digital mixing the adc and dac data can be combined in various ways to support a range of different usage modes. data from either of the two adcs can be routed to either the left or the right channel of the digital audio interface. in addition, data from either of the digital audio interface channels can be routed to either the left or the right dac. see "digital audio interface" for more information on the audio interface. digital mixing paths figure 28 shows the digital mixing paths available in the wm8991 digital core. adcdat adclrc/gpio1 bclk dacdat daclrc gpio5/dacdat2 gpio6/adclrcb gpio2/mclk2 gpio3/bclk2 gpio4/daclrc2 gpio alternative dac interface alternative mclk button control / accessory detect clock output inverted adclrc adcr_ena high pass filter (voice or hi-fi) high pass filter (voice or hi-fi) 0 0 dac dac adc adc + mono dac_boost [1:0] adcl_datinv adc_hpf_cut [1:0] adcl_vol [7:0] adcr_vol [7:0] dacl_vol [7:0] dacr_vol [7:0] adc_to_dacl [1:0] adc_to_dacr [1:0] dac_mono dac_mute, dac_mutemode, dac_muterate, dac_sb_filt, deemp[1:0] dacl dacr en en dac_boost 00 = 0db 01 = +6db 10 = +12db 11 = +18db 00=0 01=adcl 10=adcr 11=reserved digital audio interface a-law and u-law support tdm support adc_hpf_ena en en adcl_dac_svol [3:0] adcr_dac_svol [3:0] adcr_datinv dacr_datinv dacl_datinv aifadcl_src aifadcr_src l r dacr_src dacl_src r l + + en en adcl_ena digital core readback available main register bit reference register bit also referenced elsewhere in diagram figure 28 digital mixing paths
wm8991 production data w pd, december 2008, rev 4.0 58 the polarity of each adc output signal can be changed under software control using the adcl_datinv and adcr_datinv register bits. the aifadcl_src and aifadcr_src register bits may be used to select which adc is used for the left and right digital audio interface data. these register bits are described in table 19. register address bit label default description r4 (04h) 15 aifadcl_src 0b left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 14 aifadcr_src 1b right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel r14 (0eh) 1 adcl_datinv 0b left adc invert 0 = left adc output not inverted 1 = left adc output inverted 0 adcr_datinv 0b right adc invert 0 = right adc output not inverted 1 = right adc output inverted table 19 adc routing and control the input data source for each dac can be changed under software control using register bits dacl_src and dacr_src. the polarity of each dac input may also be modified using register bits dacl_datinv and dacr_datinv. these register bits are described in table 20. register address bit label default description r5 (05h) 15 dacl_src 0b left dac data source select 0 = left dac outputs left channel data 1 = left dac outputs right channel data 14 dacr_src 1b right dac data source select 0 = right dac outputs left channel data 1 = right dac outputs right channel data r10 (0ah) 1 dacl_datinv 0b left dac invert 0 = left dac output not inverted 1 = left dac output inverted 0 dacr_datinv 0b right dac invert 0 = right dac output not inverted 1 = right dac output inverted table 20 dac routing and control
production data wm8991 w pd, december 2008, rev 4.0 59 dac interface volume boost a digital gain function is available at the audio interface to boost the dac volume when a small signal is received on dacdat. this is controlled using register bits dac_boost[1:0]. to prevent clipping at the dac input, this function should not be used when the boosted dac data is expected to be greater than 0dbfs. register address bit label default description r5 (05h) 11:10 dac_boost [1:0] 00b dac input volume boost 00 = 0db 01 = +6db (input data must not exceed -6dbfs) 10 = +12db (input data must not exceed -12dbfs) 11 = +18db (input data must not exceed -18dbfs) table 21 dac interface volume boost digital sidetone a digital sidetone is available when adcs and dacs are operating at the same sample rate. digital data from either left or right adc can be mixed with the audio interface data on the left and right dac channels. sidetone data is taken from the adc high pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). the digital sidetone will not function when adcs and dacs are operating at different sample rates. when using the digital sidetone, it is recommended that the adcs are enabled before un-muting the dacs to prevent pop noise. the dac volumes and sidetone volumes should be set to an appropriate level to avoid clipping at the dac input. the digital sidetone is controlled as shown in table 22. register address bit label default description r13 (0dh) 12:9 adcl_dac_svol [3:0] 0000b left digital sidetone volume (see table 23 for volume range) 8:5 adcr_dac_svol [3:0] 0000b right digital sidetone volume (see table 23 for volume range) 3:2 adc_to_dacl [1:0] 00b left dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved 1:0 adc_to_dacr [1:0] 00b right dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved table 22 digital sidetone control
wm8991 production data w pd, december 2008, rev 4.0 60 adcl_dac_svol or a dcr_dac_svol sidetone v olume 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 0 1110 0 1111 0 table 23 digital sidetone volume
production data wm8991 w pd, december 2008, rev 4.0 61 digital to analogue converter (dac) the wm8991 dacs receive digital input data from the dacdat pin and via the digital sidetone path. the digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters two multi-bit, sigma-delta dacs, which convert them to high quality analogue audio signals. the multi-bit dac architecture reduces high frequency noise and sensitivity to clock jitter. it also uses a dynamic element matching technique for high linearity and low distortion. the analogue outputs from the dacs can then be mixed with other analogue inputs using the output mixers lomix, romix and the speaker output mixer spkmix. the dacs are enabled by the dacl_ena and dacr_ena register bits. register address bit label default description r3 (03h) 1 dacl_ena (rw) 0b left dac enable 0 = dac disabled 1 = dac enabled 0 dacr_ena (rw) 0b right dac enable 0 = dac disabled 1 = dac enabled table 24 dac enable control dac digital volume control the output level of each dac can be controlled digitally over a range from -71.625db to 0db in 0.375db steps. the level of attenuation for an eight-bit code x is given by: 0.375 (x-192) db for 1 x 192; mute for x = 0 0db for 192 x 255 the dac_vu bit controls the loading of digital volume control data. when dac_vu is set to 0, the dacl_vol or dacr_vol control data will be loaded into the respective control register, but will not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to dac_vu. this makes it possible to update the gain of both channels simultaneously. register address bit label default description r11 (0bh) 8 dac_vu n/a dac volume update writing a 1 to this bit will cause left and right dac volume to be updated simultaneously 7:0 dacl_vol [7:0] 1100_0000b (0db) left dac digital volume (see table 26 for volume range) r12 (0ch) 8 dac_vu n/a dac volume update writing a 1 to this bit will cause left and right dac volume to be updated simultaneously 7:0 dacr_vol [7:0] 1100_0000b (0db) right dac digital volume (see table 26 for volume range) table 25 dac digital volume control
wm8991 production data w pd, december 2008, rev 4.0 62 dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.000 2h -71.250 42h -47.250 82h -23.250 c2h 0.000 3h -70.875 43h -46.875 83h -22.875 c3h 0.000 4h -70.500 44h -46.500 84h -22.500 c4h 0.000 5h -70.125 45h -46.125 85h -22.125 c5h 0.000 6h -69.750 46h -45.750 86h -21.750 c6h 0.000 7h -69.375 47h -45.375 87h -21.375 c7h 0.000 8h -69.000 48h -45.000 88h -21.000 c8h 0.000 9h -68.625 49h -44.625 89h -20.625 c9h 0.000 ah -68.250 4ah -44.250 8ah -20.250 cah 0.000 bh -67.875 4bh -43.875 8bh -19.875 cbh 0.000 ch -67.500 4ch -43.500 8ch -19.500 cch 0.000 dh -67.125 4dh -43.125 8dh -19.125 cdh 0.000 eh -66.750 4eh -42.750 8eh -18.750 ceh 0.000 fh -66.375 4fh -42.375 8fh -18.375 cfh 0.000 10h -66.000 50h -42.000 90h -18.000 d0h 0.000 11h -65.625 51h -41.625 91h -17.625 d1h 0.000 12h -65.250 52h -41.250 92h -17.250 d2h 0.000 13h -64.875 53h -40.875 93h -16.875 d3h 0.000 14h -64.500 54h -40.500 94h -16.500 d4h 0.000 15h -64.125 55h -40.125 95h -16.125 d5h 0.000 16h -63.750 56h -39.750 96h -15.750 d6h 0.000 17h -63.375 57h -39.375 97h -15.375 d7h 0.000 18h -63.000 58h -39.000 98h -15.000 d8h 0.000 19h -62.625 59h -38.625 99h -14.625 d9h 0.000 1ah -62.250 5ah -38.250 9ah -14.250 dah 0.000 1bh -61.875 5bh -37.875 9bh -13.875 dbh 0.000 1ch -61.500 5ch -37.500 9ch -13.500 dch 0.000 1dh -61.125 5dh -37.125 9dh -13.125 ddh 0.000 1eh -60.750 5eh -36.750 9eh -12.750 deh 0.000 1fh -60.375 5fh -36.375 9fh -12.375 dfh 0.000 20h -60.000 60h -36.000 a0h -12.000 e0h 0.000 21h -59.625 61h -35.625 a1h -11.625 e1h 0.000 22h -59.250 62h -35.250 a2h -11.250 e2h 0.000 23h -58.875 63h -34.875 a3h -10.875 e3h 0.000 24h -58.500 64h -34.500 a4h -10.500 e4h 0.000 25h -58.125 65h -34.125 a5h -10.125 e5h 0.000 26h -57.750 66h -33.750 a6h -9.750 e6h 0.000 27h -57.375 67h -33.375 a7h -9.375 e7h 0.000 28h -57.000 68h -33.000 a8h -9.000 e8h 0.000 29h -56.625 69h -32.625 a9h -8.625 e9h 0.000 2ah -56.250 6ah -32.250 aah -8.250 eah 0.000 2bh -55.875 6bh -31.875 abh -7.875 ebh 0.000 2ch -55.500 6ch -31.500 ach -7.500 ech 0.000 2dh -55.125 6dh -31.125 adh -7.125 edh 0.000 2eh -54.750 6eh -30.750 aeh -6.750 eeh 0.000 2fh -54.375 6fh -30.375 afh -6.375 efh 0.000 30h -54.000 70h -30.000 b0h -6.000 f0h 0.000 31h -53.625 71h -29.625 b1h -5.625 f1h 0.000 32h -53.250 72h -29.250 b2h -5.250 f2h 0.000 33h -52.875 73h -28.875 b3h -4.875 f3h 0.000 34h -52.500 74h -28.500 b4h -4.500 f4h 0.000 35h -52.125 75h -28.125 b5h -4.125 f5h 0.000 36h -51.750 76h -27.750 b6h -3.750 f6h 0.000 37h -51.375 77h -27.375 b7h -3.375 f7h 0.000 38h -51.000 78h -27.000 b8h -3.000 f8h 0.000 39h -50.625 79h -26.625 b9h -2.625 f9h 0.000 3ah -50.250 7ah -26.250 bah -2.250 fah 0.000 3bh -49.875 7bh -25.875 bbh -1.875 fbh 0.000 3ch -49.500 7ch -25.500 bch -1.500 fch 0.000 3dh -49.125 7dh -25.125 bdh -1.125 fdh 0.000 3eh -48.750 7eh -24.750 beh -0.750 feh 0.000 3fh -48.375 7fh -24.375 bfh -0.375 ffh 0.000 table 26 dac digital volume range
production data wm8991 w pd, december 2008, rev 4.0 63 dac soft mute and soft un-mute the wm8991 has a soft mute function which, when enabled, gradually attenuates the volume of the dac output. when soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gain setting, depending on the dac_mutemode register bit. the dac is soft-muted by default (dac_mute = 1). to play back an audio signal, this function must first be disabled by setting dac_mute to 0. soft mute mode would typically be enabled (dac_mutemode = 1) when using dac_mute during playback of audio data so that when dac_mute is subsequently disabled, the sudden volume increase will not create pop noise by jumping immediately to the previous volume level (e.g. resuming playback after pausing during a track). soft mute mode would typically be disabled (dac_mutemode = 0) when un-muting at the start of a music file, in order that the first part of the track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). dac muting and un-muting using volume control bits dacl_vol and dacr_vol. dac muting and un-muting using soft mute bit dac_mute. soft mute mode not enabled (dac_mutemode = 0). dac muting and un-muting using soft mute bit dac_mute. soft mute mode enabled (dac_mutemode = 1). figure 29 dac mute control the volume ramp rate during soft mute and un-mute is controlled by the dac_muterate bit. ramp rates of fs/32 and fs/2 are selectable as shown in table 27. the ramp rate determines the rate at which the volume will be increased or decreased. the actual ramp time depends on the extent of the difference between the muted and un-muted volume settings. register address bit label default description r10 (0ah) 7 dac_muterate 0b dac soft mute ramp rate 0 = fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) 6 dac_mutemode 0b dac soft mute mode 0 = disabling soft-mute (dac_mute=0) will cause the dac volume to change immediately to dacl_vol and dacr_vol settings 1 = disabling soft-mute (dac_mute=0) will cause the dac volume to ramp up gradually to the dacl_vol and dacr_vol settings 2 dac_mute 1b dac soft mute control 0 = dac un-mute 1 = dac mute table 27 dac soft-mute control
wm8991 production data w pd, december 2008, rev 4.0 64 dac mono mix a dac digital mono-mix mode can be enabled using the dac_mono register bit. this mono mix will be output on the enabled dacs. to prevent clipping, a -6db attenuation is automatically applied to the mono mix. register address bit label default description r10 (0ah) 9 dac_mono 0b dac mono mix 0 = stereo 1 = mono (mono mix output on enabled dacs) table 28 dac mono mix dac de-emphasis digital de-emphasis can be applied to the dac playback data (e.g. when the data comes from a cd with pre-emphasis used in the recording). de-emphasis filtering is available for sample rates of 48khz, 44.1khz and 32khz. see "digital filter characteristics" section for details of de-emphasis filter characteristics. register address bit label default description r10 (0ah) adc and dac control (1) 5:4 deemp [1:0] 00b dac de-emphasis control 00 = no de-emphasis 01 = 32khz sample rate 10 = 44.1khz sample rate 11 = 48khz sample rate table 29 dac de-emphasis control dac sloping stopband filter two dac filter types are available, selected by the register bit dac_sb_filt. when operating at lower sample rates (e.g. during voice communication) it is recommended that the sloping stopband filter type is selected (dac_sb_filt=1) to reduce out-of-band noise which can be audible at low dac sample rates. see "digital filter characteristics" section for details of dac filter characteristics. register address bit label default description r10 (0ah) 8 dac_sb_filt 0b selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode table 30 dac sloping stopband filter
production data wm8991 w pd, december 2008, rev 4.0 65 output signal path the wm8991 output routing and mixers provide a high degree of flexibility, allowing operation of many simultaneous signal paths through the device to various analogue outputs. the outputs provide many combinations of headphone, loudspeaker and single-ended line drivers. see ?analogue outputs? for further details of these outputs. the wm8991 output signal paths and control registers are illustrated in figure 30. figure 30 control registers for output signal path
wm8991 production data w pd, december 2008, rev 4.0 66 output signal paths enable the output mixers and drivers can be independently enabled and disabled as described in table 31. note that the headphone outputs lout and rout have dedicated volume controls. as a result, the output pgas lopga and ropga do not need to be enabled to provide volume control for the lout and rout outputs. register address bit label default description r3 (03h) 13 lon_ena (rw) 0b lon line out and lonmix enable 0 = disabled 1 = enabled 12 lop_ena (rw) 0b lop line out and lopmix enable 0 = disabled 1 = enabled 11 ron_ena (rw) 0b ron line out and ronmix enable 0 = disabled 1 = enabled 10 rop_ena (rw) 0b rop line out and ropmix enable 0 = disabled 1 = enabled 8 spkpga_ena (rw) 0b spkmix mixer and speaker pga enable 0 = disabled 1 = enabled note that spkmix and s pkpga are also enabled when spk_ena is set. 7 lopga_ena (rw) 0b lopga left volume control enable 0 = disabled 1 = enabled 6 ropga_ena (rw) 0b ropga right volume control enable 0 = disabled 1 = enabled 5 lomix_ena (rw) 0b lomix left output mixer enable 0 = disabled 1 = enabled 4 romix_ena (rw) 0b romix right output mixer enable 0 = disabled 1 = enabled r1 (01h) 12 spk_ena (rw) 0b spkmix mixer, speaker pga and speaker output enable 0 = disabled 1 = enabled 11 out3_ena (rw) 0b out3 and out3mix enable 0 = disabled 1 = enabled 10 out4_ena (rw) 0b out4 and out4mix enable 0 = disabled 1 = enabled 9 lout_ena (rw) 0b lout (left headphone output) enable 0 = disabled 1 = enabled 8 rout_ena (rw) 0b rout (right headphone output) enable 0 = disabled 1 = enabled table 31 output signal paths enable
production data wm8991 w pd, december 2008, rev 4.0 67 output mixer control the output mixer volume controls are described in table 32 for the left channel and table 33 for the right channel. the gain of each of analogue input paths may be controlled independently in the range described in table 34. the dac input levels may be controlled by the dac digital volume control - see ?digital to analogue converter (dac)? for further details of this control. register address bit label default description r45 (2dh) 5 lri3lo 0b rin3 to lomix mute 0 = mute 1 = un-mute r45 (2dh) 4 lli3lo 0b lin3 to lomix mute 0 = mute 1 = un-mute r49 (31h) 8:6 lri3lovol [2:0] 000b rin3 to lomix volume (see table 34 for volume range) r47 (2fh) 8:6 lli3lovol [2:0] 000b lin3 to lomix volume (see table 34 for volume range) r45 (2dh) 2 ll12lo 0b lin12 pga output to lomix mute 0 = mute 1 = un-mute r47 (2fh) 2:0 ll12lovol [2:0] 000b lin12 pga output to lomix volume (see table 34 for volume range) r45 (2dh) 3 lr12lo 0 rin12 pga output to lomix mute 0 = mute 1 = un-mute r47 (2fh) 5:3 lr12lovol [2:0] 000b rin12 pga output to lomix volume (see table 34 for volume range) r45 (2dh) 7 lrblo 0b ainrmux output (right adc bypass) to lomix mute 0 = mute 1 = un-mute r49 (31h) 5:3 lrblovol [2:0] 000b ainrmux output (right adc bypass) to lomix volume (see table 34 for volume range) r45 (2dh) 6 llblo 0b ainlmux output (left adc bypass) to lomix mute 0 = mute 1 = un-mute r49 (31h) 2:0 llblovol [2:0] 000b ainlmux output (left adc bypass) to lomix volume (see table 34 for volume range) r45 (2dh) 0 ldlo 0b left dac to lomix mute 0 = mute 1 = un-mute note: ldlo must be muted when ldspk=1 table 32 left output mixer (lomix) volume control
wm8991 production data w pd, december 2008, rev 4.0 68 register address bit label default description r46 (2eh) 5 rli3ro 0b lin3 to romix mute 0 = mute 1 = un-mute r46 (2eh) 4 rri3ro 0b rin3 to romix mute 0 = mute 1 = un-mute r50 (32h) 8:6 rli3rovol [2:0] 000b lin3 to romix volume (see table 34 for volume range) r48 (30h) 8:6 rri3rovol [2:0] 000b rin3 to romix volume (see table 34 for volume range) r46 (2eh) 3 rl12ro 0b lin12 pga output to romix mute 0 = mute 1 = un-mute r48 (30h) 5:3 rl12rovol [2:0] 000b lin12 pga output to romix volume (see table 34 for volume range) r46 (2eh) 2 rr12ro 0b rin12 pga output to romix mute 0 = mute 1 = un-mute r48 (30h) 2:0 rr12rovol [2:0] 000b rin12 pga output to romix volume (see table 34 for volume range) r46 (2eh) 7 rlbro 0b ainlmux output (left adc bypass) to romix mute 0 = mute 1 = un-mute r50 (32h) 5:3 rlbrovol [2:0] 000b ainlmux output (left adc bypass) to romix volume (see table 34 for volume range) r46 (2eh) 6 rrbro 0b ainrmux output (right adc bypass) to romix 0 = mute 1 = un-mute r50 (32h) 2:0 rrbrovol [2:0] 000b ainrmux output (right adc bypass) to romix volume (see table 34 for volume range) r46 (2eh) 0 rdro 0b right dac to romix mute 0 = mute 1 = un-mute note: rdro must be muted when rdspk=1 table 33 right output mixer (romix) volume control
production data wm8991 w pd, december 2008, rev 4.0 69 volume setting volume (db) 000 0 001 -3 010 -6 011 -9 100 -12 101 -15 110 -18 111 -21 table 34 lomix and romix volume range output signal path volume control the output drivers lopga, ropga, lout and rout can be independently controlled as shown in table 35 and table 36. to minimise pop noise it is recommended that only the lopgavol, ropgavol, loutvol and routvol are modified while the output signal path is active. other gain controls are provided in the output signal path to provide appropriate relative scaling of signals from different sources, and to prevent clipping when multiple signals are mixed. to prevent pop noise, only the gain controls noted above should be modified while playback is active. to prevent "zipper noise", a zero-cross function is provided on these output paths, so that when enabled, volume updates will not take place until a zero-crossing is detected. in the event of a long period without zero-crossings, a timeout function is available. when this function is enabled (using the toclk_ena register bit), the volume will update after the timeout period if no earlier zero-cross has occurred. the timeout period is set by toclk_rate. see ?clocking and sample rates? for more information on these fields. the opvu bit controls the loading of the output driver volume data. when opvu is set to 0, the volume control data will be loaded into the respective control register, but will not actually change the gain setting. the lopga, ropga, lout and rout volume settings are all updated when a 1 is written to opvu. this makes it possible to update the gain of all output paths simultaneously. note that the headphone outputs lout and rout have dedicated volume controls. as a result, the output pgas lopga and ropga do not need to be enabled to provide volume control for the lout and rout outputs.
wm8991 production data w pd, december 2008, rev 4.0 70 register address bit label default description r32 (20h) 8 opvu[2] n/a output pga volume update writing a 1 to this bit will update lopga, ropga, loutvol and routvol volumes simultaneously. 7 lopgazc 0b lopga zero cross enable 0 = zero cross disabled 1 = zero cross enabled 6:0 lopgavol [6:0] 79h (0db) lopga volume (see table 36 for output pga volume control range) r33 (21h) 8 opvu[3] n/a output pga volume update writing a 1 to this bit will update lopga, ropga, loutvol and routvol volumes simultaneously. 7 ropgazc 0b ropga zero cross enable 0 = zero cross disabled 1 = zero cross enabled 6:0 ropgavol [6:0] 79h (0db) ropga volume (see table 36 for output pga volume control range) r28 (1ch) 8 opvu[0] n/a output pga volume update writing a 1 to this bit will update lopga, ropga, loutvol and routvol volumes simultaneously. 7 lozc 0b lout (left headphone output) zero cross enable 0 = zero cross disabled 1 = zero cross enabled 6:0 loutvol [6:0] 00h (mute) lout (left headphone output) volume (see table 36 for output pga volume control range) r29 (1dh) 8 opvu[1] n/a output pga volume update writing a 1 to this bit will update lopga, ropga, loutvol and routvol volumes simultaneously. 7 rozc 0b rout (right headphone output) zero cross enable 0 = zero cross disabled 1 = zero cross enabled 6:0 routvol [6:0] 00h (mute) rout (right headphone output) volume (see table 36 for output pga volume control range) table 35 lopga, ropga, lout and rout volume control
production data wm8991 w pd, december 2008, rev 4.0 71 lopgavol, ropgavol, loutvol, routvol or spkvol volume (db) lopgavol, ropgavol, loutvol, routvol or spkvol volume (db) 0h mute 40h -57 1h mute 41h -56 2h mute 42h -55 3h mute 43h -54 4h mute 44h -53 5h mute 45h -52 6h mute 46h -51 7h mute 47h -50 8h mute 48h -49 9h mute 49h -48 ah mute 4ah -47 bh mute 4bh -46 ch mute 4ch -45 dh mute 4dh -44 eh mute 4eh -43 fh mute 4fh -42 10h mute 50h -41 11h mute 51h -40 12h mute 52h -39 13h mute 53h -38 14h mute 54h -37 15h mute 55h -36 16h mute 56h -35 17h mute 57h -34 18h mute 58h -33 19h mute 59h -32 1ah mute 5ah -31 1bh mute 5bh -30 1ch mute 5ch -29 1dh mute 5dh -28 1eh mute 5eh -27 1fh mute 5fh -26 20h mute 60h -25 21h mute 61h -24 22h mute 62h -23 23h mute 63h -22 24h mute 64h -21 25h mute 65h -20 26h mute 66h -19 27h mute 67h -18 28h mute 68h -17 29h mute 69h -16 2ah mute 6ah -15 2bh mute 6bh -14 2ch mute 6ch -13 2dh mute 6dh -12 2eh mute 6eh -11 2fh mute 6fh -10 30h -73 70h -9 31h -72 71h -8 32h -71 72h -7 33h -70 73h -6 34h -69 74h -5 35h -68 75h -4 36h -67 76h -3 37h -66 77h -2 38h -65 78h -1 39h -64 79h 0 3ah -63 7ah 1 3bh -62 7bh 2 3ch -61 7ch 3 3dh -60 7dh 4 3eh -59 7eh 5 3fh -58 7fh 6 table 36 lopga, ropga, lout, rout and spkvol volume range
wm8991 production data w pd, december 2008, rev 4.0 72 the speaker mixer spkmix, the speaker pga spkpga and the outputs spkn and spkp are controlled as described in table 37. care should be taken to avoid clipping when enabling more than one path to the speaker mixer. register bits spkattn control the speaker output attenuation and can be used to avoid clipping when more than one full scale signal is input to the mixer. fine adjustment of the speaker output can be made using the spkvol register field. to prevent "zipper noise" when adjusting the spkvol, a zero-cross function is provi ded so that, when enabled, volume updates will not take place until a zero-crossing is detected. in the event of a long period without zero-crossings, a timeout function is available. when this function is enabled (using the toclk_ena register bit), the volume will update after the timeout period if no earlier zero- cross has occurred. the timeout period is set by toclk_rate. see ?clocking and sample rates? for more information on these fields. register address bit label default description r54 (36h) 7 lb2spk 0b ainlmux output to spkmix 0 = mute 1 = un-mute 6 rb2spk 0b ainrmux output to spkmix 0 = mute 1 = un-mute 5 li2spk 0b lin2 to spkmix 0 = mute 1 = un-mute 4 ri2spk 0b rin2 to spkmix 0 = mute 1 = un-mute 3 lopgaspk 0b lopga to spkmix 0 = mute 1 = un-mute 2 ropgaspk 0b ropga to spkmix 0 = mute 1 = un-mute 1 ldspk 0b left dac to spkmix 0 = mute 1 = un-mute note: ldspk must be muted when ldlo=1 0 rdspk 0b right dac to spkmix 0 = mute 1 = un-mute note: rdspk must be muted w hen rdro=1 r34 (22h) 1:0 spkattn [1:0] 11b speaker output attenuation ( spkn and spkp) 00 = 0db 01 = -6db 10 = -12db 11 = mute r38 (26h) 7 spkzc 0b spkpga zero cross e nable 0 = zero cross disabled 1 = zero cross enabled 6:0 spkvol [6:0] 79h (0db) spkpga volume (see table 36 for spkpga volume control range) table 37 speaker output volume control
production data wm8991 w pd, december 2008, rev 4.0 73 the output mixers out3mix and out4mix and their outputs out3 and out4 are controlled as described in table 38. care should be taken to avoid clipping when enabling more than one path to out3 or out4. the out3attn and out4attn attenuation controls can be used to prevent clipping when more than one full scale signal is input to the mixers. register address bit label default description r31 (1fh) 5 out3mute 1b out3 mute 0 = un-mute 1 = mute 4 out3attn 0b out3 attenuation 0 = 0db 1 = -6db 1 out4mute 1b out4 mute 0 = un-mute 1 = mute 0 out4attn 0b out4 attenuation 0 = 0db 1 = -6db r51 (33h) 5 li4o3 0b lin4/rxn pin to out3mix 0 = mute 1 = un-mute 4 lpgao3 0b lopga to out3mix 0 = mute 1 = un-mute 1 ri4o4 0b rin4/rxp pin to out4mix 0 = mute 1 = un-mute 0 rpgao4 0b ropga to out4mix 0 = mute 1 = un-mute table 38 out3 and out4 volume control
wm8991 production data w pd, december 2008, rev 4.0 74 the output mixers lopmix and lonmix and their outputs lop and lon are controlled as described in table 39. care should be taken to avoid clipping when enabling more than one path to lop or lon. the loattn attenuation control can be used to prevent clipping when more than one full scale signal is input to the lop mixer. register address bit label default description r30 (1eh) 6 lonmute 1b lon line output mute 0 = un-mute 1 = mute 5 lopmute 1b lop line output mute 0 = un-mute 1 = mute 4 loattn 0b lop attenuation 0 = 0db 1 = -6db r52 (34h) 6 llopgalon 0b lopga to lonmix 0 = mute 1 = un-mute 5 lropgalon 0b ropga to lonmix 0 = mute 1 = un-mute 4 loplon 0b inverted lop output to lonmix 0 = mute 1 = un-mute 2 lr12lop 0b rin12 pga output to lopmix 0 = mute 1 = un-mute 1 ll12lop 0b lin12 pga output to lopmix 0 = mute 1 = un-mute 0 llopgalop 0b lopga to lopmix 0 = mute 1 = un-mute table 39 lop and lon volume control
production data wm8991 w pd, december 2008, rev 4.0 75 the output mixers ropmix and ronmix and their outputs rop and ron are controlled as described in table 40. care should be taken to avoid clipping when enabling more than one path to rop or ron. the roattn attenuation control can be used to prevent clipping when more than one full scale signal is input to the rop mixer. register address bit label default description r30 (1eh) 2 ronmute 1b ron line output mute 0 = un-mute 1 = mute 1 ropmute 1b rop line output mute 0 = un-mute 1 = mute 0 roattn 0b rop attenuation 0 = 0db 1 = -6db r53 (35h) 6 rropgaron 0b ropga to ronmix 0 = mute 1 = un-mute 5 rlopgaron 0b lopga to ronmix 0 = mute 1 = un-mute 4 ropron 0b inverted rop output to ronmix 0 = mute 1 = un-mute 2 rl12rop 0b lin12 pga output to ropmix 0 = mute 1 = un-mute 1 rr12rop 0b rin12 pga output to ropmix 0 = mute 1 = un-mute 0 rropgarop 0b ropga to ropmix 0 = mute 1 = un-mute table 40 rop and ron volume control
wm8991 production data w pd, december 2008, rev 4.0 76 analogue outputs the speaker, headphone and line outputs are highly configurable and may be used in many different ways. speaker output configurations the speaker outputs spkp and spkn are driven by the s peaker mixer spkmix, and speaker volume control spkpga, which can output a mix that is any combination of the following signals: ? left dac and right dac outputs ? lomix and romix outputs via volume controls lopga and ropga ? line inputs lin2 and rin2 ? output from left and right input mixers (ainlmux & ainrmux) the speaker mixer is controlled as described under ?output signal path?. the speaker mixer output can be attenuated to avoid clipping when mixing multiple signal inputs. fine adjustment of the speaker output can be made by the speaker volume control s pkpga. the speaker outputs spkp and spkn operate in a btl configuration in class ab and class d amplifier modes. the mode is selected by register bit cdmode. the outputs are capable of driving 1w into an 8 btl load (or 500mw in class ab mode for thermal reasons) at room temperature. for performance at higher temperatures, see figure 2 in the ?recommended operating conditions? section. ultra-low leakage and high psrr allow the speaker supply spkvdd to be directly connected to a lithium battery. six levels of ac and dc signal boost are provided in order to deliver maximum output power for many commonly-used spkvdd/avdd combinations. these boost options are available in both class ab and class d modes. the ac and dc gain levels from 1.0x to 1.8x are selected using register bits acgain and dcgain. to prevent pop noise, dcgain and acgain should not be modified while the speaker outputs are enabled. note that an appropriate spkvdd s upply voltage must be provided to prevent waveform clipping when speaker boost is used. figure 31 speaker boost operation spkp spkn spkattn[1:0] spkvol[6:0] a cgain[2:0] spkgnd spkvdd agnd a vdd dcgain[2:0] or acgain[2:0] 000 = 1.00 x 001 = 1.27 x 010 = 1.40 x 011 = 1.52 x 100 = 1.67 x 101 = 1.80 x vmid avdd a gnd dcgain[2:0] vmid x dcgain vmid x dcgain spkvdd signal x acgain btl connection provides an additional 6db gain speaker mixe r
production data wm8991 w pd, december 2008, rev 4.0 77 register address bit label default description r35 (23h) 8 cdmode 0b speaker class d mode enable 0 = class d mode 1 = class ab mode r37 (25h) 5:3 dcgain [2:0] 000b (1.0x) dc speaker boost 000 = 1.00x boost (+0db) 001 = 1.27x boost (+2.1db) 010 = 1.40x boost (+2.9db) 011 = 1.52x boost (+3.6db) 100 = 1.67x boost (+4.5db) 101 = 1.80x boost (+5.1db) 110 to 111 = reserved 2:0 acgain [2:0] 000b (1.0x) ac speaker boost 000 = 1.00x boost (+0db) 001 = 1.27x boost (+2.1db) 010 = 1.40x boost (+2.9db) 011 = 1.52x boost (+3.6db) 100 = 1.67x boost (+4.5db) 101 = 1.80x boost (+5.1db) 110 to 111 = reserved table 41 speaker boost control headphone output configurations the headphone outputs lout, rout, out3 and out4 are each driven by different output mixers as described below. the lout and rout pins output the lomix and romix outputs respectively. the output mixer out3mix produces an output out3 that is a combination of: ? lin4/rxn ? lomix output via volume control lopga the output mixer out4mix produces an output out4 that is a combination of: ? rin4/rxp ? romix output via volume control ropga full volume control is available on lout and rout. 0db and -6db attenuation is available on out3 and out4, with full volume control available using lopga and ropga for the lomix and romix signals. the outputs lout, rout, out3 and out4 are capable of driving 40mw into 16 loads such as stereo headsets, headphones, and/or a handset ear speaker. ac-coupled, capless mode and fully differential headphone drive modes are available. ac-coupled output is possible on each of lout, rout, out3 and out4 simultaneously. capless headphone output is possible on lout and rout by using either out3 or out4 as the common return path. (this is achieved by muting out3 or out4 as required.) if rxp and rxn are a mono differential input (e.g. a connection to an external voice codec), then out3 and out4 may be used as a differential output capable of driving a handset ear speaker. the signal paths from rxp to out4 and from rxn to out3 are direct, and do not pass through any additional amplifiers. this reduces standby and active power consumption and improves signal quality.
wm8991 production data w pd, december 2008, rev 4.0 78 when driving a handset ear speaker using out3 and out4 other than from rxp/rxn, the required phase difference can be provided by inverting one of the dac outputs or alternatively by mixing left and right channels together using either lomix or romix and muting the opposite channel. note that a differential output will provide an additional 6db gain at the output pins. register bits out3attn and out4attn can be used to compensate for this gain if required. fully differential headphone drive is possible between lout and out3 and between rout and out4. routing lopga to out3 and ropga to out4 results in a phase inversion at lout with respect to out3 and at rout with respect to out4. this allows fully differential headset drive, with greatly improved crosstalk performance, improved bass response, increased noise immunity and removing the need for large and expensive dc-blocking capacitors. to ensure fully balanced differential operation, lout and out3 must be set to the same gain as each other, and rout and out4 must be set to the same gain as each other. this is best achieved by setting out3attn and out4attn to 0db, whilst setting volume controls lopgavol and loutvol at matching levels and setting volume controls ropgavol and routvol at matching levels. some example headphone output configurations are shown below. figure 32 ac-coupled headphone drive figure 33 capless mode headphone drive figure 34 headphone and ear speaker drive figure 35 fully differential headphone drive
production data wm8991 w pd, december 2008, rev 4.0 79 line output configurations the line outputs lon, lop, ron and rop are each driven by different output mixers as described below. the lop and rop pins output a mix of lin12 input pga, rin12 input pga and either lomix or romix outputs. the lon output is a mix of romix, lomix and a phase-inverted copy of lop. the ron output is a mix of lomix, romix and a phase-inverted copy of rop. volume control of lomix and romix is available in all cases above via lopga and ropga. an additional -6db attenuation option is provided on lop and rop outputs. the outputs lon, lop, ron and rop are capable of driving line loads only. single ended output is possible on all these output simultaneously. differential output is also possible between lop and lon and between rop and ron. typical applications for the line outputs (single-ended or differential) are: ? handset or headset microphone output to external voice codec ? stereo line output ? output to external speaker driver(s) to support stereo loudspeakers some example line output configurations are shown below. -1 figure 36 stereo line out (a) figure 37 differential output of mic pga -1 -1 figure 38 stereo line out (b) figure 39 differential output to speaker driver
wm8991 production data w pd, december 2008, rev 4.0 80 -1 -1 -1 -1 figure 40 stereo line out (c) figure 41 stereo differential line out
production data wm8991 w pd, december 2008, rev 4.0 81 disabled outputs whenever an analogue output is disabled, it can be connected to vref through a resistor; this feature is enabled by setting the bufioen bit ? see ?pop suppression control?. this helps to prevent pop noise when the output is re-enabled. the resistance between vref and each output can be controlled using register bit vroi. by default, a high resistance is used - 20k for headphone outputs (lout, rout, out3 and out4) and 10k for line outputs (lon, lop, ron and rop). if a low impedance is desired for disabled outputs, vroi can then be set to 1, decreasing the resistance to about 500 in all cases. note that a disabled output may be used as a common ground connection for a capless headphone output as described earlier. register address bit label default description r55 (37h) additional control 0 vroi 0 vref to analogue output resistance (disabled outputs) 0 = 20k (headphone) or 10k (line out) from buffered vmid to output 1 = 500 from buffered vmid to output table 42 disabled outputs to vref resistance thermal shutdown the speaker and headphone outputs can drive very large currents. to protect the wm8991 from overheating a thermal shutdown circuit is included. if the device temperature reaches approximately 150oc and the thermal shutdown circuit is enabled (tshut_ena = 1; tshut_opdis = 1) the speaker and headphone amplifiers (lout, rout, spkp, spkn, out3 and out4) will be disabled. tshut_ena must be set to 1 to enable the temperature sensor when using the tshut_opdis thermal shutdown function. the output of the temperature sensor can also be output to the gpio pins. register address bit label default description r2 (02h) 14 tshut_ena (rw) 1b thermal sensor enable 0 = thermal sensor disabled 1 = thermal sensor enabled 13 tshut_opdis (rw) 1b thermal shutdown enable (requires thermal sensor to be enabled) 0 = thermal shutdown disabled 1 = thermal shutdown enabled table 43 thermal shutdown when the speaker driver is operating in class ab mode the internal power dissipation of the wm8991 is likely to be significantly higher than when operating in class d mode. note: to prevent potential pops and clicks thsut_ena and tshut_opdis need to be configured while the speaker and headphone outputs are off, i.e. lout_ena, rout_ena, out3_ena, out4_ena and spk_ena are 0 (see also table 79).
wm8991 production data w pd, december 2008, rev 4.0 82 general purpose input/output the wm8991 provides a number of versatile gpio functions to enable features such as mobile tv support, wi-fi voice call recording, button and accessory detection and clock output. the wm8991 has eight multi-purpose pins for these functions. ? gpio1 to gpio6: dedicated gpio pins. ? lin3/gpi7 and rin3/gpi8: analogue inputs or button/accessory detect inputs. the following functions are available on some or all of the gpio pins. ? alternative dac interface (dacdat, daclrc, bclk) ? button detect (latched with programmable de-bounce) ? micbias / accessory current or short circuit detect ? alternative mclk input ? clock output ? inverted adclrc output ? temperature sensor output ? pll lock output ? logic '1' and logic '0' output ? interrupt event output ? serial data output (register readback) the functions available on each of the gpio pins are identified in table 44. gpio pin function gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpi7 gpi8 adclrc y mclk2 y bclk2 y daclrc2 y dacdat2 y adclrcb y button/accessory detect inputyyyyyyyy clock output yyyyyy temperature ok yyyyyy pll lock yyyyyy logic 1 and logic 0 y y y y y y interrupt yyyyyy sdout (readback data) yyyyyy pull-up & pull-down available y y y y y y gpio pins table 44 functions available on gpio pins the gpio pins are configured by a combination of register settings described in table 45 to table 48 in the following section. the order of precedence for the control of the gpio pins is as listed below. 1. pin pull-up or pull-down (gpion_pu, gpion_pd) 2. audio interface and gpio tristate (aif_tris) 3. pin configuration (aifsel, mclk_src, alrcgpio1, and alrcbgpio6) 4. gpio functionality (gpion_sel)
production data wm8991 w pd, december 2008, rev 4.0 83 gpio control registers table 45 shows how the dual-function gpio pins are configured to operate in their different modes. note that the order of precedence described earlier applies. register field aif_sel selects the function of gpio3, gpio4 and gpio5 between audio interface 2 and gpio functions. register field alrcgpio1 enables the gpio functionality on gpio1. register field mclk_src enables the gpio functionality on gpio2. register field alrcgpio6 enables the inverted adclrc output on gpio6. register bit aif_tris, when set, takes precedence over aif_sel, alrcgpio1, mclk_src and alrcbgpio6 and tri-states all gpio pins. register address bit label default description r7 (07h) 15 mclk_src 0b mclk source select 0 = mclk pin 1 = gpio2/mclk2 pin r8 (08h) 13 aif_sel 0b audio interface select 0 = audio interface 1 1 = audio interface 2 (gpio3/bclk2, gpio4/daclrc2, gpio5/dacdat2) r9 (09h) 15 alrcgpio1 0b adclrc/gpio1 pin function select 0 = adclrc 1 = gpio1 (adclrc connected to daclrc internally) 14 alrcbgpio6 0b gpio6/adclrcb pin function select 0 = gpio6 1 = inverted adclrc clock output 13 aif_tris 0b audio interface and gpio tristate 0 = audio interface and gpio pins operate normally 1 = tristate all audio interface and gpio pins table 45 gpio and gpi pin function select the gpio pins are also controlled by the register fields described in table 46. note the order of precedence described earlier applies. pull-up and pull-down resistors may be enabled on any of gpio1 to gpio6. if enabled, these settings take precedence over all other gpio selections for that pin. note that, by default, the pull- down resistors on gpio2, gpio3, gpio4, gpio5 and gpio6 are enabled. when the gpio pins are used as inputs, de-bounce and interrupt masking may be controlled on all gpio pins (including gpi7 and gpi8) using gpion_deb_ena and gpion_irq_ena bits as shown in table 47. for each of gpio1 to gpio6, the register field gpion_sel is used to select the pin functions of the individual gpio pins as shown in table 47. note that this control has the lowest precedence and is only effective when gpion_pu, gpion_pd, aif_tris, aifsel, mclk_src, alrcgpio1 and alrcbgpio6 are set to allow gpio functionality on that gpio pin.
wm8991 production data w pd, december 2008, rev 4.0 84 register address bit label default description r19 (13h) 15 gpio2_deb_ena 0b see table 47 for gpio2 control bit description 14 gpio2_irq_ena 0b 13 gpio2_pu 0b 12 gpio2_pd 1b 11:8 gpio2_sel[3:0] 0000b 7 gpio1_deb_ena 0b see table 47 for gpio1 control bit description 6 gpio1_irq_ena 0b 5 gpio1_pu 0b 4 gpio1_pd 0b 3:0 gpio1_sel[3:0] 0000b r20 (14h) 15 gpio4_deb_ena 0b see table 47 for gpio4 control bit description 14 gpio4_irq_ena 0b 13 gpio4_pu 0b 12 gpio4_pd 1b 11:8 gpio4_sel[3:0] 0000b 7 gpio3_deb_ena 0b see table 47 for gpio3 control bit description 6 gpio3_irq_ena 0b 5 gpio3_pu 0b 4 gpio3_pd 1b 3:0 gpio3_sel[3:0] 0000b r21 (15h) 15 gpio6_deb_ena 0b see table 47 for gpio6 control bit description 14 gpio6_irq_ena 0b 13 gpio6_pu 0b 12 gpio6_pd 1b 11:8 gpio6_sel[3:0] 0000b 7 gpio5_deb_ena 0b see table 47 for gpio5 control bit description 6 gpio5_irq_ena 0b 5 gpio5_pu 0b 4 gpio5_pd 1b 3:0 gpio5_sel[3:0] 0000b r22 (16h) 7 gpi8_deb_ena 0b see table 47 for gpin control bit description 6 gpi8_irq_ena 0b 4 gpi8_ena 0b 3 gpi7_deb_ena 0b see table 47 for gpin control bit description 2 gpi7_irq_ena 0b 0 gpi7_ena 0b table 46 gpio and gpi control
production data wm8991 w pd, december 2008, rev 4.0 85 the following table describes the coding of the fields listed in table 46. register address label default description registers r19 (13h) to r21 (15h) (see table 46) gpion_deb_ena (n = 1 to 8) 0b de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena = 1) gpion_irq_ena (n = 1 to 8) 0b irq enable 0 = disabled 1 = enabled gpion_pu (n = 1 to 6) 0b gpio pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ) gpion_pd (n = 1 to 6) see table 46 gpio pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k ) gpion_sel[3:0] (n = 1 to 6) 0000b gpion pin function select 0000 = input pin 0001 = clock output (sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved gpin_ena (n = 7 or 8) 0b gpin input pin enable 0 = pin disabled as gpin input 1 = pin enabled as gpin input table 47 gpio function control bits the polarity of gpio/gpi inputs may be configured using the gpio_pol register bits. this is described in table 48. register address bit label default description r23 (17h) 7:0 gpio_pol [7:0] (rw) 00h gpion input polarity 0 = non-inverted 1 = inverted gpio_pol[7] = gpi8 polarity gpio_pol[6] = gpi7 polarity gpio_pol[5] = gpio6 polarity gpio_pol[4] = gpio5 polarity gpio_pol[3] = gpio4 polarity gpio_pol[2] = gpio3 polarity gpio_pol[1] = gpio2 polarity gpio_pol[0] = gpio1 polarity table 48 gpio polarity each of the available gpio functions is described in turn in the following sections.
wm8991 production data w pd, december 2008, rev 4.0 86 alternative dac interface the wm8991 may be configured to select between two different audio interfaces, providing the capability to receive dac input data via bclk2, daclrc2 and dacdat2 instead of bclk, daclrc and dacdat. this selection is made by register bit aif_sel, as described in table 45. to use the alternative dac interface, the following register settings are required: ? aif_tris = 0 ? aif_sel = 1 ? gpio3_pu = 0, gpio4_pu = 0, gpio5_pu = 0 ? gpio3_pd = 0, gpio4_pd = 0, gpio5_pd = 0 note that additional devices can also be connected to the main interface pins using the tdm mode. see "digital audio interface" section for further details on controlling the audio interface pins. the alternative dac interface connection is illustrated in figure 42. adcdat adclrc/gpio1 bclk dacdat daclrc gpio5/dacdat2 gpio6/adclrcb digital audio interface a-law and u-law support tdm support gpio2/mclk2 gpio3/bclk2 gpio4/daclrc2 gpio alternative dac interface alternative mclk button control / accessory detect clock output inverted adclrc processor #2 processor #1 aif_sel figure 42 alternative dac interface
production data wm8991 w pd, december 2008, rev 4.0 87 button control the wm8991 gpio supports button control detection with full status readback for up to seven inputs (and one irq output). all inputs are latched at the irq register, with de-bounce available for normal operation. de-bouncing may be disabled in order to allow the device to respond to wake-up events while the processor is disabled and is unable to provide a clock for de-bouncing. to enable button control and accessory detection, the following register settings are required: ? alrcgpio1 = 1 (only required if using gpio1) ? mclk_src = 0 (only required if using gpio2) ? aif_sel = 0 (only required if using gpio3, gpio4 or gpio5) ? alrcgpio6 = 0 (only required if using gpio6) ? lmn3 = 0, lli3lo = 0 and rli3lo = 0 (only required if using gpi7) ? rmn3 = 0, rri3lo = 0 and lri3ro = 0 (only required if using gpi8) ? aif_tris = 0 ? gpion_sel = 0000 for each required gpio button input programmable pull-up and pull-down resistors are available on gpio1 to gpio6. these should be set according to the external circuit configuration. note that pull-up and pull-down resistors are not available on the gpi7 and gpi8 input pins. note that the analogue input paths to gpi7 and gpi8 must be disabled as described above when using these as digital inputs. in this application, one or more of the gpio pins may be configured as an interrupt event if desired. this is controlled by the gpion_irq_ena bits described in table 46. the gpio pin status fields contained in the irq register (r18) may be read at any time or else in response to an interrupt event. see table 55 for more details of the interrupt function. an example configuration of the button control gpio function is illustrated in figure 43. figure 43 example of button control using gpio pins note: ? the gpios 1 to 6 are referenced to dbvdd ? the gpis 7 and 8 are referenced to avdd
wm8991 production data w pd, december 2008, rev 4.0 88 micbias current and accessory detect a micbias current detect function is provided for accessory detection. when a microphone current is detected (e.g. when a headset is inserted), an interrupt event can be generated and the microphone status read back via the control interface. the micbias current detect threshold is programmable. a short-circuit current detection is also available, with a programmable threshold. these functions are enabled by register bit mcd; the thresholds are programmable via register fields mcdthr and mcdsctr as shown in table 49. current detect and short circuit detect thresholds are subject to a +/- 30% temperature, supply and part-to-part variation. this should be factored into any application design. the polarity of the current detect gpio signals may be controlled by register bits micdet_pol and micshrt_pol. note that these polarity inversion bits apply to the interrupt register behaviour only; they do not affect the direct gpio output of the current detect functions. the respective interrupt events may be masked or enabled by register bits micdet_irq_ena and micshrt_irq_ena. the micbias current threshold status bits contained in the irq register (r18) may be read at any time or else in response to an interrupt event. see table 55 for more details of the interrupt function. if direct output of the micbias current detect function is required to the external pins of the wm8991, the following register settings are required: ? alrcgpio1 = 1 (only required if using gpio1) ? mclk_src = 0 (only required if using gpio2) ? aif_sel = 0 (only required if using gpio3, gpio4 or gpio5) ? alrcgpio6 = 0 (only required if using gpio6) ? aif_tris = 0 ? gpion_sel = 1000 for the selected gpio micbias current detect output pin ? gpion_sel = 1001 for the selected gpio micbias short circuit detect output pin ? gpion_pu = 0 for the selected gpio micbias output pin or pins ? gpion_pd = 0 for the selected gpio micbias output pin or pins
production data wm8991 w pd, december 2008, rev 4.0 89 the register fields used to configure the micbias current detect function are described in table 49. register address bit label default description r58 (3ah) 7:6 mcdscth [1:0] 00b micbias short circuit detect threshold 00 = 600ua 01 = 1200ua 10 = 1800ua 11 = 2400ua these values are for avdd=3.3v and scale proportionally with avdd. 5:3 mcdthr [2:0] 000b micbias current detect threshold 000 = 200ua 001 = 350ua 010 = 500ua 011 = 650ua 100 = 800ua 101 = 950ua 110 = 1100ua 111 = 1250ua these values are for avdd=3.3v and scale proportionally with avdd. 2 mcd 0b micbias current and short circuit detect enable 0 = disabled 1 = enabled r23 (17h) 10 micshrt_pol (rw) 0b micbias short circuit detect polarity 0 = non-inverted 1 = inverted 9 micdet_pol (rw) 0b micbias current detect polarity 0 = non-inverted 1 = inverted r22 (16h) 10 micshrt_irq_ena 0b micbias short circuit detect irq enable 0 = disabled 1 = enabled 9 micdet_irq_ena 0b micbias current detect irq enable 0 = disabled 1 = enabled table 49 micbias current detect control the current detect function operates according to the following the truth table: label value description mic short circuit detect 0 mcdscth current threshold not exceeded mic short circuit detect 1 mcdscth current threshold exceeded mic current detect 0 mcdthr current threshold not exceeded mic current detect 1 mcdthr current threshold exceeded table 50 truth table for gpio output of micbias current detect function
wm8991 production data w pd, december 2008, rev 4.0 90 alternative mclk input an alternative mclk source can be input via the mclk2/gpio2 pin. this provides additional flexibility for systems where the codec is required to interface with more than one processor. see "clocking and sample rates" for more information on selecting mclk source. to enable the alternative mclk input on gpio2, the following register settings are required: ? mclk_src = 1 ? aif_tris = 0 ? gpio2_pu = 0 ? gpio2_pd = 0 ? gpio2_sel = 0000 the above register fields are described in table 45 and table 46. clock output a clock output (opclk) derived from sysclk may be output via gpio1 to gpio6. sysclk is derived from mclk (either directly, or in conjunction with the pll), and is used to provide all internal clocking for the wm8991 (see "clocking and sample rates" section for more information). a programmable clock divider opclkdiv controls the frequency of the opclk output. this clock is enabled by register bit opclk_ena. see ?clocking and sample rates? for a definition of this register field. to enable clock output via one or more gpio pins, the following register settings are required: ? alrcgpio1 = 1 (only required if using gpio1) ? mclk_src = 0 (only required if using gpio2) ? aif_sel = 0 (only required if using gpio3, gpio4 or gpio5) ? alrcgpio6 = 0 (only required if using gpio6) ? aif_tris = 0 ? gpion_sel = 0001 for the selected gpio clock output pin ? gpion_pu = 0 for the selected gpio clock output pin ? gpion_pd = 0 for the selected gpio clock output pin inverted adclrc output an inverted adclrc signal can be output via the gpio6/adclrcb pin. to enable the inverted adclrc output, the following register settings are required: ? alrcgpio6 = 1 ? aif_tris = 0 ? gpio6_pu = 0 ? gpio6_pd = 0
production data wm8991 w pd, december 2008, rev 4.0 91 temperature sensor output the wm8991 output drivers can generate a large amount of heat. to protect the device from overheating a thermal shutdown function is provided (see "thermal shutdown" section for more information). the polarity of the thermal shutdown sensor may be controlled by register bit tempok_pol. note that this polarity inversion bit applies to the interrupt register behaviour only; it does not affect the direct gpio output of the temperature sensor function. the associated interrupt event may be masked or enabled by register bit tempok_irq_ena. the temperature status bit contained in the irq register (r18) may be read at any time or else in response to an interrupt event. see table 55 for more details of the interrupt function. if direct output of the temperature status bit is required to the external pins of the wm8991, the following register settings are required: ? alrcgpio1 = 1 (only required if using gpio1) ? mclk_src = 0 (only required if using gpio2) ? aif_sel = 0 (only required if using gpio3, gpio4 or gpio5) ? alrcgpio6 = 0 (only required if using gpio6) ? aif_tris = 0 ? gpion_sel = 0101 for the selected gpio temperature status output pin ? gpion_pu = 0 for the selected gpio temperature status output pin ? gpion_pd = 0 for the selected gpio temperature status output pin the register fields used to configure the temperature sensor gpio function are described in table 51. register address bit label default description r23 (17h) 11 tempok_pol (rw) 1b temperature sensor polarity 0 = non-inverted 1 = inverted r22 (16h) 11 tempok_irq_ ena 0b temperature sensor irq enable 0 = disabled 1 = enabled table 51 temperature sensor gpio control the temperature sensor function operates according to the following truth table: label value description temperature sensor output 0 overheat temperature exceeded temperature sensor output 1 overheat temperature not exceeded table 52 truth table for gpio output of temperature sensor function
wm8991 production data w pd, december 2008, rev 4.0 92 pll lock output an internal signal used to indicate the lock status of the pll can be output to a gpio pin or used to trigger an interrupt event. the polarity of the pll lock indication may be controlled by register bit pll_lck_pol. note that this polarity inversion bit applies to the interrupt register behaviour only; it does not affect the direct gpio output of the pll lock function. the associated interrupt event may be masked or enabled by register bit pll_lck_irq_ena. the pll lock status bit in the irq register (r18) may be read at any time or else in response to an interrupt event. see table 55 for more details of the interrupt function. if direct output of the pll lock status bit is required to the external pins of the wm8991, the following register settings are required: ? alrcgpio1 = 1 (only required if using gpio1) ? mclk_src = 0 (only required if using gpio2) ? aif_sel = 0 (only required if using gpio3, gpio4 or gpio5) ? alrcgpio6 = 0 (only required if using gpio6) ? aif_tris = 0 ? gpion_sel = 0100 for the selected pll lock status output pin ? gpion_pu = 0 for the selected pll lock status output pin ? gpion_pd = 0 for the selected pll lock status output pin the register fields used to configure the pll lock gpio function are described in table 53. register address bit label default description r23 (17h) 8 pll_lck_pol (rw) 0b pll lock polarity 0 = non-inverted 1 = inverted r22 (16h) 8 pll_lck_irq_ ena 0b pll lock irq enable 0 = disabled 1 = enabled table 53 pll lock gpio control the pll lock function operates according to the following truth table: label value description pll lock output 0 pll not locked pll lock output 1 pll locked table 54 truth table for gpio output of pll lock function
production data wm8991 w pd, december 2008, rev 4.0 93 logic '1' and logic '0' output the gpio pins can be programmed to drive a logic high or logic low signal. the following register settings are required: ? alrcgpio1 = 1 (only required if using gpio1) ? mclk_src = 0 (only required if using gpio2) ? aif_sel = 0 (only required if using gpio3, gpio4 or gpio5) ? alrcgpio6 = 0 (only required if using gpio6) ? aif_tris = 0 ? gpion_sel = 0010 for each logic ?0? output pin ? gpion_sel = 0011 for each logic ?1? output pin ? gpion_pu = 0 for each logic ?0? or logic ?1? gpio pin ? gpion_pd = 0 for each logic ?0? or logic ?1? gpio pin
wm8991 production data w pd, december 2008, rev 4.0 94 interrupt event output an interrupt can be generated by any of the following events described earlier: ? button control input (on gpio1 to gpio6, gpi7 and gpi8) ? micbias current / short circuit / accessory detect ? pll lock ? temperature sensor the interrupt status flag irq is asserted when any un-masked interrupt input is asserted. it is the or?d combination of all the un-masked interrupt inputs. if required, this flag may be inverted using the irq_inv register bit. the gpio pins can be configured to output the irq signal. the interrupt behaviour is driven by level detection (not edge detection) of the un-masked inputs. therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt status flag irq will be triggered again even though no transition has occurred. if edge detection is required (eg. confirming that the input has been de-asserted), then the polarity inversion may be used after each event in order to detect each rising and falling edge separately. this is described further in the ?gpio summary? section. the status of the irq flag may be read back via the control interface. the status of each gpio pin and the internal signals pll_lck, tempok, micshrt and micdet may also be read back in the same way. the irq register (r18) is described in table 55. the status of the gpio pins or other interrupt inputs can be read back via the read/write bits r18[11:0]. the interrupt inputs are latched once set. each input may be reset by writing a 1 to the appropriate bit. the irq bit cannot be reset; it is the or?d combination of all other registers and will reset only if r18[11:0] are all 0. if direct output of the interrupt signal is required to external pins of the wm8991, the following register settings are required: ? alrcgpio1 = 1 (only required if using gpio1) ? mclk_src = 0 (only required if using gpio2) ? aif_sel = 0 (only required if using gpio3, gpio4 or gpio5) ? alrcgpio6 = 0 (only required if using gpio6) ? aif_tris = 0 ? gpion_sel = 0111 for the selected interrupt (irq) output pin ? gpion_pu = 0 for the selected interrupt (irq) output pin ? gpion_pd = 0 for the selected interrupt (irq) output pin
production data wm8991 w pd, december 2008, rev 4.0 95 the irq register (r18) is described in table 55. register address bit label default description r18 (12h) 12 irq (ro) read only irq readback (allows polling of irq status) 11 tempok (rr) read or reset temperature ok status read- 0 = device temperature not ok 1 = device temperature ok write - 1 = reset tempok latch 10 micshrt (rr) read or reset micbias short status read- 0 = micbias ok 1 = micbias shorted write- 1 = reset micshrt latch 9 micdet (rr) read or reset micbias detect status micbias microphone detect readback read- 0 = no microphone detected 1 = microphone detected write- 1 = reset micdet latch 8 pll_lck (rr) read or reset pll lock status read- 0 = pll not locked 1 = pll locked write- 1 = reset pll_lck latch 7:0 gpio_status [7:0] (rr) read or reset gpio and gpi input pin status gpio_status[7] = gpi8 pin status gpio_status[6] = gpi7 pin status gpio_status[5] = gpio6 status gpio_status[4] = gpio5 status gpio_status[3] = gpio4 status gpio_status[2] = gpio3 status gpio_status[1] = gpio2 status gpio_status[0] = gpio1 status r23 (17h) gpio control (2) 12 irq_inv (rw) 0b irq invert 0 = irq output active high 1 = irq output active low table 55 gpio interrupt and status readback
wm8991 production data w pd, december 2008, rev 4.0 96 serial data output (register readback) the gpio pins can be configured to output serial data during register readback in 3-wire (open-drain) or 4-wire mode. the readback mode is configured using the register bits rd_3w_ena and mode_3w4w as described in table 56. setting the rd_3w_ena bit to 1 enables 3-wire readback using the sdin pin in open-drain mode. setting the rd_3w_ena bit to 0 requires the use of a gpio pin as sdout. to enable sdout on a gpio pin, the following register settings are required: ? alrcgpio1 = 1 (only required if using gpio1) ? mclk_src = 0 (only required if using gpio2) ? aif_sel = 0 (only required if using gpio3, gpio4 or gpio5) ? alrcgpio6 = 0 (only required if using gpio6) ? aif_tris = 0 ? gpion_sel = 0110 for the selected sdout output pin ? gpion_pu = 0 for the selected sdout output pin ? gpion_pd = 0 for the selected sdout output pin the register fields used to configure sdout on the gpio pins are described in table 56. refer to ?control interface? for more details of 3-wire and 4-wire interfacing. register address bit label default description r22 (16h) 15 rd_3w_ena 1b 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using gpio pin 14 mode_3w4w 0b 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-or table 56 gpio 3-wire readback enable
production data wm8991 w pd, december 2008, rev 4.0 97 gpio summary the gpio functions are summarised in figure 44. figure 44 gpio control diagram
wm8991 production data w pd, december 2008, rev 4.0 98 details of the gpio implementation are shown below. in order to avoid gpio loops if a gpio is configured as an output the corresponding input is disabled, as shown in figure 45 below. figure 45 gpio pad the gpio register, i.e. latch structure, is shown in figure 46 below. the de-bounce control fields gpion_deb_ena determine whether the signal is de-bounced or not. (note that toclk (via sysclk) needs to be present in order for the debounce circuit to work.) the polarity bits gpio_pol[7:0] control whether an interrupt is triggered by a logic 1 level (for gpio_pol[n] = 0) or a logic 0 level (for gpio_pol[n] = 1). the latch will cause the interrupt to be stored until it is reset by writing to the interrupt register. the latched signal is processed by the irq circuit, shown in figure 44 above. the interrupt status bits can be read at any time from register r18 (see table 55) and are reset by writing a ?1? to the applicable bit in register r18. note that the interrupt behaviour is driven by level detection (not edge detection). therefore, if an input remains asserted after the interrupt register has been reset, then the interrupt event will be triggered again even though no transition has occurred. if edge detection is required, this may be implemented as described in the following paragraphs. figure 46 gpio function three typical scenarios are presented in the following figure 47, figure 48 and figure 49. the examples are: ? latch a gpio input (figure 47) ? debounce and latch a gpio input (figure 48) ? use the gpion_pol bit to implement an irq edge detect function (figure 49)
production data wm8991 w pd, december 2008, rev 4.0 99 the gpio input or internal interrupt event (eg. micbias current detect) is latched as illustrated below: figure 47 gpio latch the de-bounce function on the gpio input pins enables transient behaviour to be filtered as illustrated below: figure 48 gpio de-bounce to implement an edge detect function on a gpio input, the gpion_pol bits may be used to alternate the gpio polarity after each edge transition. for example, after a logic 1 has caused an interrupt event, the polarity may be inverted prior to resetting the interrupt register bit. in this way, the next interrupt event generated by this gpio will occur when it returns to the logic 0 state. the gpion_pol bit must be reversed after every gpio edge transition, as illustrated below: figure 49 gpio edge detect
wm8991 production data w pd, december 2008, rev 4.0 100 gpio irq handling in the following diagram figure 50 a typical irq scenario is illustrated. figure 50 gpio irq handling
production data wm8991 w pd, december 2008, rev 4.0 101 digital audio interface the digital audio interface is used for inputting dac data to the wm8991 and outputting adc data from it. it uses five pins: ? adcdat: adc data output ? adclrc: adc data alignment clock (an inverted adclrc is also available via gpio) ? dacdat: dac data input (an alternative dacdat is also available via gpio) ? daclrc: dac data alignment clock (an alternative daclrc is also available via gpio) ? bclk: bit clock, for synchronisation (an alte rnative bclk is also available via gpio) the clock signals bclk, adclrc and daclrc can be outputs when the wm8991 operates as a master, or inputs when it is a slave (see master and slave mode operation, below). adclrc can also be configured as a gpio pin. in this case, the adc will use daclrc as a frame clock. the adclrc/gpio1 pin function should not be modified while the adc is enabled. dacdat, daclrc and bclk functions can also be supported using gpio pins. an inverted adclrc can also be output via gpio pins. four different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp mode all four of these modes are msb first. they are described in audio data formats, below. refer to the ?electrical characteristics? section for timing information. time division multiplexing (tdm) is available in all four data format modes. the wm8991 can be programmed to send and receive data in one of two time slots. pcm operation is supported using the dsp mode. master and slave mode operation the wm8991 digital audio interface can operate as a master or slave as shown in figure 51 and figure 52. figure 51 master mode figure 52 slave mode operation with adclrc as gpio when the adclrc/gpio1 pin is configured as a gpio pin (alrcgpio=1), the daclrc pin is used as a frame clock for adcs and dacs as shown in figure 53 and figure 54. the adcs and dacs must operate at the same sample rate in this configuration.
wm8991 production data w pd, december 2008, rev 4.0 102 figure 53 master mode with adclrc as gpio figure 54 slave mode with adclrc as gpio operation with alternative dac interface to allow data to be input to the wm8991 dacs from two separate sources, the gpio[5:3] pins can be configured as an alternative dac interface (bclk2, daclrc2, dacdat2) as shown in figure 57 to figure 60. figure 55 interface 2 = master figure 56 interface 2 = slave wm8991 processor #1 adcdat adclrc dacdat daclrc bclk processor #2 daclrc2 dacdat2 bclk2 aif_mstr1=1 aif_mstr2=0 /n /n figure 57 interface 1 = master, interface 2 = master figure 58 interface 1 = master, interface 2 = slave
production data wm8991 w pd, december 2008, rev 4.0 103 figure 59 interface 1 = slave, interface 2 = master figure 60 interface 1 = slave, interface 2 = slave the dual audio interface approach of the wm8991 has been implemented in such a way that it gives the user and application as much flexibility as possible, without any restrictions built into the wm8991. this means that the application has to be carefully analysed and the wm8991 configured accordingly. in the following figure 61 and figure 62 the audio interface input flow and the output controlling are illustrated.
wm8991 production data w pd, december 2008, rev 4.0 104 audio interface bclk adclrc adcdat daclrc dacdat bclk2 daclrc2 dacdat2 adc_bclk adc_lrclk adc_data dac_bclk dac_lrclk dac_data 0 1 alrcgpio1 aif_sel 0 1 0 1 0 1 figure 61 audio interface input flow the audio interface input flow illustrated above is controlled by only two signals. these are alrcgpio1 and aif_sel. register address bit label default description r8 (08h) 13 aif_sel 0b audio interface select 0 = audio interface 1 1 = audio interface 2 (gpio3/bclk2, gpio4/daclrc2, gpio5/dacdat2) r9 (09h) 15 alrcgpio1 0b adclrc/gpio1 pin function select 0 = adclrc pin 1 = gpio1 pin (adclrc connected to daclrc internally) table 57 audio interface pin function select
production data wm8991 w pd, december 2008, rev 4.0 105 sysclk bclk adclrc adcdat daclrc dacdat bclk2 daclrc2 dacdat2 bclk generator adclrc generator daclrc generator enable enable enable > 1 aif_mstr1 adclrc_dir aif_mstr1 aif_mstr2 0 1 alrcgpio1 aif_sel > 1 aif_mstr2 daclrc_dir 0 & aif_sel 0 1 0 1 aif_sel 0 0 1 aif_sel & !(alrcgpio1 & (adcenl+adcenr)) > 1 aif_mstr1 daclrc_dir 0 0 1 dacenl+dacenr 0 1 aif_sel & !(adcenl+adcenr) 0 figure 62 audio interface output control the audio interface output control is illustrated above. the master mode control registers aif_mstr1 and aif_mstr2 as well as the left-right clock control registers adclrc_dir and daclrc_dir determine whether the wm8991 generates the according clocks and aif_sel and alrcgpio1 control registers define the pins these clocks are provided from.
wm8991 production data w pd, december 2008, rev 4.0 106 these registers are described in table 58 below. register address bit label default description r8 (08h) 15 aif_mstr1 0b audio interface 1 master mode select 0 = slave mode 1 = master mode 14 aif_mstr2 0b audio interface 2 master mode select 0 = slave mode 1 = master mode 13 aif_sel 0b audio interface select 0 = audio interface 1 1 = audio interface 2 (gpio3/bclk2, gpio4/daclrc2, gpio5/dacdat2) 11 adclrc_dir 0b adclrc direction (forces adclrc clock to be output in slave mode) 0 = adclrc normal operation 1 = adclrc clock output enabled r9 (09h) 15 alrcgpio1 0b adclrc/gpio1 pin function select 0 = adclrc pin 1 = gpio1 pin (adclrc connected to daclrc internally) 14 alrcbgpio6 0b gpio6/adclrcb pin function select 0 = gpio6 pin 1 = inverted adclrc clock output 11 daclrc_dir 0b daclrc direction (forces daclrc clock to be output in slave mode) 0 = daclrc normal operation 1 = daclrc clock output enabled table 58 audio interface output function control operation with tdm time division multiplexing (tdm) allows multiple devices to transfer data simultaneously on the same bus. the wm8991 adcs and dacs support tdm in master and slave modes, on both interfaces, and for all data formats and word lengths. tdm is enabled using register bits aifadc_tdm and aifdac_tdm. the tdm data slot is programmed using register bits aifadc_tdm_chan and aifdac_tdm_chan.
production data wm8991 w pd, december 2008, rev 4.0 107 wm8991 processor adcdat adclrc dacdat daclrc bclk adcdat adclrc dacdat daclrc bclk wm8991 or similar codec wm8991 processor wm8991 or similar codec adcdat adclrc dacdat daclrc bclk adcdat adclrc dacdat daclrc bclk figure 63 tdm with wm8991 as master figure 64 tdm with other codec as master figure 65 tdm with processor as master note: the wm8991 is a 24-bit device. if the user operates the wm8991 in 32-bit mode then the 8 lsbs will be ignored on the receiving side and not driven on the transmitting side. it is therefore recommended to add a pull-down resistor if necessary to the dacdat line and the adcdat line in tdm mode. bclk divide the bclk frequency is controlled by bclk_div. when the adcs and dacs are operating at different sample rates, bclk_div must be set appropriately to support the data rate of whichever is the faster.
wm8991 production data w pd, december 2008, rev 4.0 108 internal clock divide and phase control mechanisms ensure that the bclk, adclrc and daclrc edges will occur in a predictable and repeatable position relative to each other and to the data for a given combination of dac sample rate, adc sample rate and bclk_div settings. see ?clocking and sample rates? section for more information. audio data formats (normal mode) in right justified mode, the lsb is available on the last rising edge of bclk before a lrclk transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrclk transition. figure 66 right justified audio interface (assuming n-bit word length) in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 67 left justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next.
production data wm8991 w pd, december 2008, rev 4.0 109 figure 68 i2s justified audio interface (assuming n-bit word length) in dsp mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by aif_lrclk_inv) following a rising edge of lrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrc output will resemble the frame pulse shown in figure 69 and figure 70. in device slave mode, figure 71 and figure 72, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figure 69 dsp mode audio interface (mode a, aif_lrclk_inv=0, master) figure 70 dsp mode audio interface (mode b, aif_lrclk_inv=1, master)
wm8991 production data w pd, december 2008, rev 4.0 110 left channel right channel lrclk bclk dacdat / adcdat n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 1 bclk input word length (wl) 1/fs falling edge can occur anywhere in this area 1 bclk figure 71 dsp mode audio interface (mode a, aif_lrclk_inv=0, slave) left channel right channel lrc bclk dacdat / adcdat n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 1 bclk input word length (wl) 1/fs falling edge can occur anywhere in this area 1 bclk figure 72 dsp mode audio interface (mode b, aif_lrclk_inv=1, slave) pcm operation is supported in dsp interface mode. wm8991 adc data that is output on the left channel will be read as mono pcm data by the receiving equipment. mono pcm data received by the wm8991 will be treated as left channel data. this data may be routed to the left/right dacs as described in the ?digital input path? section. audio data formats (tdm mode) tdm is supported in master and slave mode and is enabled by register bits aif_adc_tdm and aif_dac_tdm. all audio interface data formats support time division multiplexing (tdm) for adc and dac data. two time slots are available (slot 0 and slot 1), selected by register bits aifadc_tdm_chan and aifdac_tdm_chan which control time slots for the adc data and the dac data. when tdm is enabled, the adcdat pin will be tri-stated immediately before and immediately after data transmission, to allow another adc device to drive this signal line for the remainder of the sample period. note that it is important that two adc devices do not attempt to drive the data pin simultaneously. a short circuit may occur if the transmission time of the two adc devices overlap with each other. see ?audio interface timing - tdm mode? for details of the adcdat output relative to bclk signal. note that it is possible to ensure a gap exists between transmissions by setting the transmitted word length to a value higher than the actual length of the data. for example, if 32-bit word length is selected where only 24-bit data is available, then the wm8991 interface will tri-state after transmission of the 24-bit data, ensuring a gap after the wm8991?s tdm slot. when tdm is enabled, bclk frequency must be high enough to allow data from both time slots to be transferred. the relative timing of slot 0 and slot 1 depends upon the selected data format as shown in figure 74 to figure 77.
production data wm8991 w pd, december 2008, rev 4.0 111 figure 73 tdm in right-justified mode figure 74 tdm in left-justified mode figure 75 tdm in i 2 s mode
wm8991 production data w pd, december 2008, rev 4.0 112 figure 76 tdm in dsp mode a figure 77 tdm in dsp mode b
production data wm8991 w pd, december 2008, rev 4.0 113 digital audio interface control the register bits controlling audio data format, word length, left/right channel data source and tdm are summarised in table 59. register address bit label defaul t description r4 (04h) 15 aifadcl_src 0b left adc data source select 0 = left adc data is output on left channel 1 = right adc data is output on left channel 14 aifadcr_src 1b right adc data source select 0 = left adc data is output on right channel 1 = right adc data is output on right channel 13 aifadc_tdm 0b adc tdm enable 0 = normal adcdat operation 1 = tdm enabled on adcdat 12 aifadc_tdm_ chan 0b adcdat tdm channel select 0 = adcdat outputs data on slot 0 1 = adcdat output data on slot 1 8 aif_bclk_inv 0b bclk invert 0 = bclk not inverted 1 = bclk inverted 7 aif_lrclk_in v 0b right, left and i 2 s modes ? lrclk polarity 0 = normal lrclk polarity 1 = invert lrclk polarity dsp mode ? mode a/b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 6:5 aif_wl [1:0] 10b digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits note - see ?companding? for the selection of 8-bit mode 4:3 aif_fmt [1:0] 10b digital audio interface format 00 = right justified 01 = left justified 10 = i 2 s format 11 = dsp mode r5 (05h) 15 dacl_src 0b left dac data source select 0 = left dac outputs left channel data 1 = left dac outputs right channel data 14 dacr_src 1b right dac data source select 0 = right dac outputs left channel data 1 = right dac outputs right channel data 12 aifdac_tdm 0b dac tdm enable 0 = normal dacdat operation 1 = tdm enabled on dacdat 13 aifdac_tdm_ chan 0b dacdat tdm channel select 0 = dacdat data input on slot 0 1 = dacdat data input on slot 1 table 59 audio data format control
wm8991 production data w pd, december 2008, rev 4.0 114 audio interface output and gpio tristate register bit aif_tris can be used to tristate the audio interface and gpio pins as described in table 60. all gpio[6:1] pins and digital audio interface pins will be tristated by this function, regardless of the state of other registers which control these pin configurations. register address bit label default description r9 (09h) 13 aif_tris 0 audio interface and gpio tristate 0 = audio interface and gpio pins operate normally 1 = tristate all audio interface and gpio pins table 60 tri-stating the audio interface and gpio pins master mode bclk, adclrc and daclrc enable the main audio interface pins (bclk, adclrc, adcdat, daclrc and dacdat) and the alternative dac interface pins (bclk2, daclrc2, dacdat2) can be independently programmed to operate in master mode or slave mode using register bits aif_mstr1 and aif_mstr2. when the main audio interface is operating in slave mode, the bclk, adclrc and daclrc clock outputs to these pins are by default disabled to allow the digital audio source to drive these pins. similarly, when the alternative audio interface is operating in slave mode, the bclk2 and daclrc2 clock outputs to these pins are by default disabled. it is also possible to force the adclrc, daclrc or daclrc2 to be output using register bits adclrc_dir and daclrc_dir, allowing mixed master and slave modes for the adcs or the active dac audio interface. the active audio interface is selected by register bit aif_sel. enabled clock outputs on the de-selected audio interface will output logic 0. when adclrc is configured as a gpio pin (alrcgpio1=1), the daclrc pin is used for the adcs and the dacs and will only be disabled in master mode when both adcs and both dacs are disabled. the clock generators for the audio interface are enabled according to the control signals shown in figure 78. figure 78 clock output control
production data wm8991 w pd, december 2008, rev 4.0 115 register address bit label default description r8 (08h) 15 aif_mstr1 0b audio interface 1 master mode select 0 = slave mode 1 = master mode 14 aif_mstr2 0b audio interface 2 master mode select 0 = slave mode 1 = master mode 13 aif_sel 0b audio interface select 0 = audio interface 1 1 = audio interface 2 (gpio3/bclk2, gpio4/daclrc2, gpio5/dacdat2) 11 adclrc_dir 0b adclrc direction (forces adclrc clock to be output in slave mode) 0 = adclrc normal operation 1 = adclrc clock output enabled 10:0 adclrc_rate [10:0] 040h adclrc rate adclrc clock output = bclk / adclrc_rate integer (lsb = 1) valid from 8..2047 r9 (09h) 15 alrcgpio1 0b adclrc/gpio1 pin function select 0 = adclrc pin 1 = gpio1 pin (adclrc connected to daclrc internally) 11 daclrc_dir 0b daclrc direction (forces daclrc clock to be output in slave mode) 0 = daclrc normal operation 1 = daclrc clock output enabled 10:0 daclrc_rate [10:0] 040h daclrc rate daclrc clock output = bclk / daclrc_rate integer (lsb = 1) valid from 8..2047 table 61 digital audio interface clock output control
wm8991 production data w pd, december 2008, rev 4.0 116 companding the wm8991 supports a-law and -law companding on both transmit (adc) and receive (dac) sides as shown in table 62. register address bit label default description r5 (05h) 4 dac_comp 0b dac companding enable 0 = disabled 1 = enabled 3 dac_compmode 0b dac companding type 0 = -law 1 = a-law 2 adc_comp 0b adc companding enable 0 = disabled 1 = enabled 1 adc_compmode 0b adc companding type 0 = -law 1 = a-law table 62 companding control companding involves using a piecewise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: -law (where =255 for the u.s. and japan): f(x) = ln( 1 + |x|) / ln( 1 + ) -1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) } for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) } for 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for a-law). the data will be transmitted as the first 8 msbs of data. companding converts 13 bits ( -law) or 12 bits (a-law) to 8 bits using non-linear quantization. this provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization. the companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits). 8-bit mode is selected whenever dac_comp=1 or adc_comp=1. the use of 8-bit data allows samples to be passed using as few as 8 bclk cycles per lrc frame. when using dsp mode b, 8- bit data words may be transferred consecutively every 8 bclk cycles. 8-bit mode (without companding) may be enabled by setting dac_compmode=1 or adc_compmode=1, when dac_comp=0 and adc_comp=0. bit7 bit[6:4] bit[3:0] sign exponent mantissa table 63 8-bit companded word composition
production data wm8991 w pd, december 2008, rev 4.0 117 u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 79 -law companding a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 80 a-law companding
wm8991 production data w pd, december 2008, rev 4.0 118 loopback setting the loopback register bit enables digital loopback. when this bit is set the output data from the adc audio interface is fed directly into the dac data input. register address bit label default description r5 (05h) 0 loopback 0b digital loopback function 0 = no loopback 1 = loopback enabled (adc data output is directly input to dac data input). table 64 loopback control note: 1. master mode: adc and dac left/right clo cks must be set to the same pin w hen using loopback function (alrcgpio1=1) 2. slave mode: it is recommended to set alrcgpio1=1 as well, otherwise adclrc and daclrc must be running at the same bclk rate and in phase. 3. when the digital sidetone is enabled, adc data will continue to be added to dac data when loopback is enabled
production data wm8991 w pd, december 2008, rev 4.0 119 clocking and sample rates the internal clocks for the adcs, dacs, dsp core functions, digital audio interface and class d switching amplifier are all derived from a common internal clock source, sysclk. sysclk can either be derived directly from mclk, or may be generated from a pll using mclk as an external reference. many commonly-used audio sample rates can be derived directly from typical mclk frequencies; the pll provides additional flexibility for a wide range of mclk frequencies. an alternative mclk input may be selected via the gpio2/mclk2 pin. all clock configurations must be set up before enabling playback to avoid glitches. the adc and dac sample rates are independently selectable, relative to sysclk, using adc_clkdiv and dac_clkdiv. these fields must be set according to the required sampling frequency and depending on the selected clocking mode (aif_lrclkrate). in master mode, bclk is also derived from sysclk via a programmable division set by bclk_div. in the case where the adcs and dacs are operating at different sample rates, bclk must be set according to whichever is the faster rate. the adclrc and daclrc signals do not automatically match the adc and dac sample rates; these must be configured using adclrc_rate and daclrc_rate as described under ?digital audio interface control?. a clock (opclk) derived from sysclk can be output on the gpio pins to provide clocking for other parts of the system. this clock is enabled by opclk_ena and its frequency is set by opclkdiv. a slow clock (toclk) derived from sysclk can be used to de-bounce the button/accessory detect inputs, and to set the timeout period for volume updates when zero-cross detect is used. this clock is enabled by toclk_ena and its frequency is set by toclk_rate. the class d switching amplifier requires a clock; this is derived from sysclk via a programmable divider dclkdiv. table 65 to table 71 show the clocking and sample rate controls for mclk input, bclk output (in master mode), adcs, dacs, class d outputs and gpio clock output. the overall clocking scheme for the wm8991 is illustrated in figure 81. figure 81 clocking scheme
wm8991 production data w pd, december 2008, rev 4.0 120 sysclk control the mclk_src bit is used to select the mclk source. the source may be either mclk or gpio2/mclk2. the selected source may also be inverted by setting register bit mclk_inv. note that it is not recommended to change the control bit mclk_inv while the wm8991 is processing data as this may lead to clock glitches and signal pop and clicks. the sysclk_src bit is used to select the source for sysclk. the source may be either the selected mclk source or the pll output. the selected source is divided by the sysclk pre-divider mclk_div to generate sysclk. the selected source may also be adjusted by the mclk_div divider. these register fields are described in table 65. see ?pll? for more details of the phase locked loop clock generator. the wm8991 supports glitch-free mclk and sysclk source selection. when both clock sources are running and mclk_src or sysclk_src is modified to select one of these clocks, a glitch-free clock transition will take place. the de-glitching circuit will ensure that the minimum pulse width will be no less than the pulse width of the faster of the two clock sources. when the initial clock source is to be disabled before changing to the new clock source, the clk_force bit must also be used to force the clock source transition to take place. in this case, glitch-free operation cannot be guaranteed. register address bit label default description r7 (07h) 15 mclk_src 0b mclk source select 0 = mclk pin 1 = gpio2/mclk2 pin 14 sysclk_src 0b sysclk source select 0 = mclk (or mclk2 if mclk_src=1) 1 = pll output 13 clk_force 0b forces clock source selection 0 = existing sysclk source (mclk, mclk2 or pll output) must be active when changing to a new clock source. 1 = allows existing mclk source to be disabled before changing to a new clock source. 12:11 mclk_div [1:0] 00b sysclk pre-divider. clock source (mclk, mclk2 or pll output) will be divided by this value to generate sysclk. 00 = divide sysclk by 1 01 = reserved 10 = divide sysclk by 2 11 = reserved 10 mclk_inv 0b mclk invert 0 = master clock (mclk or mclk2) not inverted 1 = master clock (mclk or mclk2) inverted table 65 mclk and sysclk control adc / dac sample rates the adc and dac sample rates are independently selectable, relative to sysclk, by setting the register fields adc_clkdiv and dac_clkdiv. these fields must be set according to the sysclk frequency, and according to the selected clocking mode. two clocking modes are provided - normal mode (aif_lrclkrate = 0) allows selection of the commonly used sample rates from typical audio system clocking frequencies (eg. 12.288mhz); usb mode (aif_lrclkrate = 1) allows many of these sample rates to be generated from a 12mhz usb clock. depending on the available clock sources, the usb mode may be used to save power by supporting 44.1khz operation without requiring the pll.
production data wm8991 w pd, december 2008, rev 4.0 121 the aif_lrclkrate field must be set as described in table 66 to ensure correct operation of internal functions according to the sysclk / fs ra tio. table 67 describes the available sample rates using four different common mclk frequencies. in normal mode, the programmable division set by adc_clkdiv must ensure that a 256 * adc fs clock is generated for the adc dsp. dac_clkdiv must ensure that a 256 * dac fs clock is generated for the dac dsp. in usb mode, the programmable division set by adc_clkdiv must ensure that a 272 * adc fs clock is generated for the adc dsp. dac_clkdiv must ensure that a 272 * dac fs clock is generated for the dac dsp. note that in usb mode, the adc / dac sample rates do not match exactly with the commonly used sample rates (e.g. 44.118 khz instead of 44.100 khz). at most, the difference is less than 0.5%. data recorded at 44.100 khz sample rate and replayed at 44.118 khz will experience a slight (sub 0.5%) pitch shift as a result of this difference. note also that the usb mode cannot be used to generate a 48khz samples rate from a 12mhz mclk; the pll should be used in this case. in low sample rate modes (eg. 8khz voice), the snr is liable to be degraded if the typical 64fs dac clocking rate is used (see figure 81). in this case, it may be possible to improve the snr by raising the dac clocking rate by setting the dac_sdmclk_rate register field, causing the dac clocking rate to be set equal to sysclk/4. the dac_clkdiv field must still be set as descri bed above to derive the correct clock for the dac dsp. in 8khz voice applications, in systems where sysclk > 256fs (or 272fs when applicable), setting dac_sdmclk_rate will result in the snr performance being improved. note that setting dac_sdmclk_rate will result in an increase in power consumption. register address bit label default description r7 (07h) 7:5 adc_clkdiv [2:0] 000b adc sample rate divider 000 = sysclk / 1.0 001 = sysclk / 1.5 010 = sysclk / 2.0 011 = sysclk / 3.0 100 = sysclk / 4.0 101 = sysclk / 5.5 110 = sysclk / 6.0 111= reserved 4:2 dac_clkdiv [2:0] 000b dac sample rate divider 000 = sysclk / 1.0 001 = sysclk / 1.5 010 = sysclk / 2.0 011 = sysclk / 3.0 100 = sysclk / 4.0 101 = sysclk / 5.5 110 = sysclk / 6.0 111= reserved r10 (0ah) 12 dac_sdmclk_r ate 0b dac clocking rate 0 = normal operation (64fs) 1 = sysclk/4 10 aif_lrclkrate 0b lrclk rate 0 = normal mode (256 * fs) 1 = usb mode (272 * fs) table 66 adc / dac sample rate control
wm8991 production data w pd, december 2008, rev 4.0 122 sysclk adc / dac sample rate divider clocking mode adc / dac sample rate 12.288 mhz 000 = sysclk / 1 normal (256 * fs) 48 khz 001 = sysclk / 1.5 32 khz 010 = sysclk / 2 24 khz 011 = sysclk / 3 16 khz 100 = sysclk / 4 12 khz 101 = sysclk / 5.5 not used 110 = sysclk / 6 8 khz 111 = reserved reserved 11.2896 mhz 000 = sysclk / 1 normal (256 * fs) 44.1 khz 001 = sysclk / 1.5 not used 010 = sysclk / 2 22.05 khz 011 = sysclk / 3 not used 100 = sysclk / 4 11. 025 khz 101 = sysclk / 5.5 8. 018 khz 110 = sysclk / 6 not used 111 = reserved reserved 12 mhz 000 = sysclk / 1 usb mode (272 * fs) 44.118 khz 001 = sysclk / 1.5 not used 010 = sysclk / 2 22. 059 khz 011 = sysclk / 3 not used 100 = sysclk / 4 11. 029 khz 101 = sysclk / 5.5 8. 021 khz 110 = sysclk / 6 not used 111 = reserved reserved 2.048 mhz 000 = sysclk / 1 normal (256 * fs) 8 khz 001 = sysclk / 1.5 not used 010 = sysclk / 2 not used 011 = sysclk / 3 not used 100 = sysclk / 4 not used 101 = sysclk / 5.5 not used 110 = sysclk / 6 not used 111 = reserved reserved table 67 adc and dac sample rates
production data wm8991 w pd, december 2008, rev 4.0 123 bclk control in master mode, bclk is derived from sysclk via a programmable division set by bclk_div, as described in table 68. bclk_div must be set to an appropriate value to ensure that there are sufficient bclk cycles to transfer the complete data words from the adcs and to the dacs. in slave mode, bclk is generated externally and appears as an input to the codec. the host device must provide sufficient bclk cycles to transfer complete data words to the adcs and dacs. note that, although the adc and dac can run at different sample rates, they share the same bit clock pin bclk. in the case where different adc / dac sample rates are used, the bclk frequency should be set according to the higher of the adc / dac bit rates. register address bit label default description r6 (06h) 4:1 bclk_div [3:0] 0100b bclk frequency (master mode) 0000 = sysclk 0001 = sysclk / 1.5 0010 = sysclk / 2 0011 = sysclk / 3 0100 = sysclk / 4 0101 = sysclk / 5.5 0110 = sysclk / 6 0111 = sysclk / 8 1000 = sysclk / 11 1001 = sysclk / 12 1010 = sysclk / 16 1011 = sysclk / 22 1100 = sysclk / 24 1101 = sysclk / 32 1110 = sysclk / 44 1111 = syscl:k / 48 table 68 bclk control opclk control a clock output (opclk) derived from sysclk may be output via gpio1 to gpio6. this clock is enabled by register bit opclk_ena, and its frequency is controlled by opclkdiv. this output of this clock is also dependent upon the gpio register settings described under ?general purpose input/output?. register address bit label default description r6 (06h) 12:9 opclkdiv [3:0] 0000b gpio output clock divider 0000 = sysclk 0001 = sysclk / 2 0010 = sysclk / 3 0011 = sysclk / 4 0100 = sysclk / 5.5 0101 = sysclk / 6 0110 = sysclk / 8 0111 = sysclk / 12 1000 = sysclk / 16 1001 to 1111 = reserved r2 (02h) 11 opclk_ena (rw) 0b gpio clock output enable 0 = disabled 1 = enabled table 69 opclk control
wm8991 production data w pd, december 2008, rev 4.0 124 class d switching clock the class d switching clock is derived from sysclk as determined by register field dclkdiv as described in table 70. this clock should be set to between 700khz and 800khz for optimum performance. the class d switching clock should not be disabled when the speaker output is active, as this will prevent the speaker outputs from functioning. the class d switching clock frequency should not be altered while the speaker output is active as this may generate an audible click. register address bit label default description r6 (06h) 8:6 dclkdiv [2:0] 111b class d clock divider 000 = sysclk 001 = sysclk / 2 010 = sysclk / 3 011 = sysclk / 4 100 = sysclk / 6 101 = sysclk / 8 110 = sysclk / 12 111 = sysclk / 16 table 70 dclk control toclk control a slow clock (toclk) is derived from sysclk to enable input de-bouncing and volume update timeout functions. this clock is enabled by register bit toclk_ena, and its frequency is controlled by toclk_rate, as described in table 71. register address bit label default description r6 (06h) 15 toclk_rate 0b timeout clock rate (selects clock to be used for volume update timeout and gpio input de- bounce) 0 = sysclk / 2 21 (slower response) 1 = sysclk / 2 19 (faster response) 14 toclk_ena 0b timeout clock enable (this clock is required for volume update timeout and gpio input de-bounce) 0 = disabled 1 = enabled table 71 toclk control usb mode it is possible to reduce power consumption by disabling the pll in some applications. one such application is when sysclk is generated from a 12mhz usb clock source. setting the aif_lrclkrate bit as described earlier (see ?adc / dac sample rates?) allows a sample rate close to 44.1khz to be generated with no additional pll power consumption. in this configuration, sysclk must be driven directly from mclk (or mclk2) and by disabling the pll. this is achieved by setting sysclk_src=0, p ll_ena=0. register address bit label default description r10 (0ah) 10 aif_lrclkrate 0b lrclk rate 0 = normal mode (256 * fs) 1 = usb mode (272 * fs) table 72 usb mode control
production data wm8991 w pd, december 2008, rev 4.0 125 pll the integrated pll can be used to generate sysclk for the wm8991 from a wide range of mclk reference frequencies. the pll is enabled by the pll_ena register bit. if required, the input reference clock can be divided by 2 by setting the register bit prescale. the pll frequency ratio r is equal to f 2 /f 1 (see figure 81). this ratio is the real number represented by register fields plln and pllk, where plln is an integer (lsb = 1) and pllk is the fractional portion of the number (msb = 0.5). the fractional portion is only valid when enabled by the field sdm. de-selection of fractional mode results in lower power consumption. for pll stability, input frequencies and divisions must be chosen so that 5 plln 13. best performance is achieved for 7 n 9. also, the pll performs best when f 2 is set between 90mhz and 100mhz. if pllk is regarded as a 16-bit integer (instead of a fractional quantity), then plln and pllk may be determined as follows: ? plln = int r ? pllk = int (2 16 (r - plln)) the pll control register settings are described in table 73. register address bit label default description r2 (02h) 15 pll_ena (rw) 0 pll enable 0 = disabled 1 = enabled r60 (3ch) 7 sdm 0 enable pll integer mode 0 = integer mode 1 = fractional mode 6 prescale 0b divide mclk by 2 at pll input 0 = divide by 1 1 = divide by 2 3:0 plln [3:0] 8h integer (n) part of pll frequency ratio. r61 (3dh) 7:0 pllk [15:8] 31h fractional (k) part of pll frequency ratio. (most significant bits) r62 (3eh) 7:0 pllk [7:0] 26h fractional (k) part of pll frequency ratio. (least significant bits) table 73 pll control
wm8991 production data w pd, december 2008, rev 4.0 126 example pll calculation to generate 12.288mhz sysclk from a 12mhz reference clock: there is a fixed divide by 4 at the pll output (see figure 81) followed by a selectable divide by 2 in the same path. pll output f 2 should be set in the range 90mhz - 100mhz. enabling the divide by 2 (mclk_div = 10b) sets the required f 2 = 4 x 2 x 12.288mhz = 98.304mhz. there is a selectable pre-scale (divide mclk by 2) at the pll input (f 1 - see figure 75). the pll frequency ratio f 2 /f 1 must be set in the range 5 - 13. disabling the mclk pre-scale (prescale = 0b) sets the required ratio f 2 /f 1 = 8.192. the required settings for this example are: ? mclk_div = 10b ? prescale = 0b ? pll_ena = 1 ? sdm = 1 ? plln = 8 = 8h ? pllk = 0.192 = 3126h example pll settings table 74 provides example pll settings for generating common sysclk fr equencies from a variety of mclk reference frequencies. mclk (mhz) sysclk (mhz) mclkdiv f2 = sysclk * 4 * mclkdiv prescale f1 = mclk/ prescale r = f2/f1 n k 12 11.2896 2 90.3168 1 12 7.5264 7h 86c2h 12 12.288 2 98.304 1 12 8.192 8h 3126h 13 11.2896 2 90.3168 1 13 6.947446 6h f28bh 13 12.288 2 98.304 1 13 7.561846 7h 8fd5h 14.4 11.2896 2 90.3168 1 14.4 6.272 6h 45a1h 14.4 12.288 2 98.304 1 14.4 6.826667 6h d3a0h 19.2 11.2896 2 90.3168 2 9.6 9.408 9h 6872h 19.2 12.288 2 98.304 2 9.6 10.24 ah 3d70h 19.68 11.2896 2 90.3168 2 9.84 9.178537 9h 2db4h 19.68 12.288 2 98.304 2 9.84 9.990243 9h fd80h 19.8 11.2896 2 90.3168 2 9.9 9.122909 9h 1f76h 19.8 12.288 2 98.304 2 9.9 9.929697 9h ee00h 24 11.2896 2 90.3168 2 12 7.5264 7h 86c2h 24 12.288 2 98.304 2 12 8.192 8h 3126h 26 11.2896 2 90.3168 2 13 6.947446 6h f28bh 26 12.288 2 98.304 2 13 7.561846 7h 8fd5h 27 11.2896 2 90.3168 2 13.5 6.690133 6h b0ach 27 12.288 2 98.304 2 13.5 7.281778 7h 4822h table 74 pll frequency examples
production data wm8991 w pd, december 2008, rev 4.0 127 control interface the wm8991 is controlled by writing to its control registers. readback is available for certain registers, including device id, power management registers and some gpio status bits. the control interface can operate as either a 2-, 3- or 4-wire control interface, with additional variants as detailed below: 1. 2-wire - open-drain 2. 3-wire - push 0/1 - open drain 3. 4-wire - push 0/1 - wired-or readback is provided on the bi-directional pin sdin in 2-/3-wire modes and on a gpio pin in 4-wire mode. selection of control mode the mode pin determines the 2- or 3-/4-wire mode as shown in table 75. mode interface format low 2 wire high 3- or 4- wire table 75 control interface mode selection 2-wire serial control mode the wm8991 is controlled by writing to registers through a 2-wire serial control interface. a control word consists of 24 bits. the first 8 bits (b23 to b16) are address bits that select which control register is accessed. the remaining 16 bits (b15 to b0) are data bits, corresponding to the 16 bits in each control register. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 8-bit address of each register in the wm8991). the default device address is 0011010 (0x34h). the wm8991 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8991, then the wm8991 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1? when operating in write only mode, the wm8991 returns to the idle condition and wait for a new start condition and valid address. the wm8991 supports a multitude of read and write operations, which are: ? single write ? single read ? multiple write using auto-increment ? multiple read using auto-increment
wm8991 production data w pd, december 2008, rev 4.0 128 these modes are shown in the section below. terminology used in the following figures: terminology description s start condition sr repeated start a acknowledge p stop condition rw readnotwrite 0 = write 1 = read table 76 terminology figure 82 2-wire serial control interface (single write) rw device id sr a p msbyte data (1) lsbyte data a device id s a index (0) a rw a figure 83 2-wire serial control interface (single read) figure 84 2-wire serial control interface (multiple write using auto-increment) figure 85 2-wire serial control interface (multiple read using auto-increment) in 2-wire mode, the wm8991 has two possible device addresses, which can be selected using the csb/addr pin. csb/addr state device address low 0011010 (0 x 34h) high 0011011 (0 x 36h) table 77 2-wire control interface address selection
production data wm8991 w pd, december 2008, rev 4.0 129 3-wire / 4-wire serial control modes the wm8991 is controlled by writing to registers through a 3- or 4-wire serial control interface. a control word consists of 24 bits. the first bit is the read/write bit (r/w), which is followed by 7 address bits (a6 to a0) that determine which control register is accessed. the remaining 16 bits (b15 to b0) are data bits, corresponding to the 16 bits in each control register. the 3- or 4-wire modes are selected by the rd_3w_ena register bit. additionally the mode_3w4w control bit can be used to select between push 0/1 and open-drain or wired-or modes, as described in table 78 below. register address bit label default description r22 (16h) 15 rd_3w_ena 1b 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using gpio pin 14 mode_3w4w 0b 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-or table 78 3-wire / 4-wire control interface selection 3-wire control mode is selected by setting rd_3w_ena = 1. in 3-wire mode, every rising edge of sclk clocks in one data bit from the sdin pin. a rising edge on csb/addr latches in a complete control word consisting of the last 24 bits. in write operations (r/w=0), all sdin bits are driven by the controlling device. in read operations (r/w=1), the sdin pin is driven by the controlling device to clock in the register address, after which the wm8991 drives the sdin pin to output the applicable data bits. the 3-wire control mode timing is illustrated in figure 86. figure 86 3-wire serial control interface 4-wire control mode is selected by setting rd_3w_ena = 0. in write operations (r/w=0), this mode is the same as 3-wire mode described above. in read operations (r/w=1), a gpio pin must be selected to output sdout by setting gpion_sel=0110b (n= 1 to 6). in this mode, the sdin pin is ignored following receipt of the valid register address. sdout is driven by the wm8991. in 4-wire push 0/1 mode, sdout is driven low when not outputting register data bits. in wired-or mode, sdout is undriven when not outputting register data bits. the 4-wire control mode timing is illustrated in figure 87 and figure 88.
wm8991 production data w pd, december 2008, rev 4.0 130 r/w a6 a5 a4 a3 a2 a1 a0 sdin sclk csb control register address control register data bits ( read / write ) sdout b15 b14 b13 b12 b11 b10 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 b15 b14 b13 b12 b11 b10 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 figure 87 4-wire readback (push 0/1) a6 a5 a4 a3 a2 a1 a0 sdin sclk csb control register address control register data bits ( read / write ) sdout undriven b15 b14 b13 b12 b11 b10 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 b15 b14 b13 b12 b11 b10 b9 b8 b0 b7 b6 b5 b4 b3 b2 b1 ud r/w figure 88 4-wire readback (wired-or)
production data wm8991 w pd, december 2008, rev 4.0 131 power management power management registers the wm8991 has three control registers that allow users to select which functions are active. for minimum power consumption, unused functions should be disabled. to minimise pop or click noise, it is important to enable or disable functions in the correct order. see ?pop suppression control? for further details of recommended control sequences. register address bit label defaul t description r1 (1h) 12 spk_ena (rw) 0b spkmix mixer, s peaker pga and speaker output enable 0 = disabled 1 = enabled 11 out3_ena (rw) 0b out3 and out3mix enable 0 = disabled 1 = enabled 10 out4_ena (rw) 0b out4 and out4mix enable 0 = disabled 1 = enabled 9 lout_ena (rw) 0b lout (left headphone output) enable 0 = disabled 1 = enabled 8 rout_ena (rw) 0b rout (right headphone output) enable 0 = disabled 1 = enabled 4 micbias_ena (rw) 0b micbias enable 0 = off (high impedance output) 1 = on 2:1 vmid_mode [1:0] (rw) 00b vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (normal mode) 10 = 2 x 250k divider (standby mode) 11 = 2 x 5k divider (for fast start-up) 0 vref_ena (rw) 0b vref enable (bias for all analogue functions) 0 = vref bias disabled 1 = vref bias enabled r2 (02h) 15 pll_ena (rw) 0b pll enable 0 = disabled 1 = enabled 14 tshut_ena (rw) 0b thermal sensor enable 0 = thermal sensor disabled 1 = thermal sensor enabled 13 tshut_opdis (rw) 1b thermal shutdown enable (requires thermal sensor to be enabled) 0 = thermal shutdown disabled 1 = thermal shutdown enabled 11 opclk_ena (rw) 0b gpio clock output enable 0 = disabled 1 = enabled 9 ainl_ena (rw) 0b left input path enable (enables ainlmux, inmixl, diffinl and rxvoice input to ainlmux) 0 = disabled 1 = enabled
wm8991 production data w pd, december 2008, rev 4.0 132 register address bit label defaul t description 8 ainr_ena (rw) 0b left input path enable (enables ainrmux, inmixr, diffinr and rxvoice input to ainrmux) 0 = disabled 1 = enabled 7 lin34_ena (rw) 0b lin34 input pga enable 0 = disabled 1 = enabled 6 lin12_ena (rw) 0b lin12 input pga enable 0 = disabled 1 = enabled 5 rin34_ena (rw) 0b rin34 input pga enable 0 = disabled 1 = enabled 4 rin12_ena (rw) 0b rin12 input pga enable 0 = disabled 1 = enabled 1 adcl_ena (rw) 0b left adc enable 0 = disabled 1 = enabled 0 adcr_ena (rw) 0b right adc enable 0 = disabled 1 = enabled r3 (03h) 13 lon_ena (rw) 0b lon line out and lonmix enable 0 = disabled 1 = enabled 12 lop_ena (rw) 0b lop line out and lopmix enable 0 = disabled 1 = enabled 11 ron_ena (rw) 0b ron line out and ronmix enable 0 = disabled 1 = enabled 10 rop_ena (rw) 0b rop line out and ropmix enable 0 = disabled 1 = enabled 8 spkpga_ena (rw) 0b spkmix mixer and speaker pga enable 0 = disabled 1 = enabled note that spkmix and spkpga are also enabled when spk_ena is set. 7 lopga_ena (rw) 0b lopga left volume control enable 0 = disabled 1 = enabled 6 ropga_ena (rw) 0b ropga right volume control enable 0 = disabled 1 = enabled 5 lomix_ena (rw) 0b lomix left output mixer enable 0 = disabled 1 = enabled 4 romix_ena (rw) 0b romix right output mixer enable 0 = disabled 1 = enabled 1 dacl_ena (rw) 0b left dac enable 0 = disabled 1 = enabled
production data wm8991 w pd, december 2008, rev 4.0 133 register address bit label defaul t description 0 dacr_ena (rw) 0b right dac enable 0 = disabled 1 = enabled table 79 power management chip reset and id the device id can be read back from register 0. writing to this register will reset the device. register address bit label default description r0 (00h) reset / id 15:0 sw_reset_ chip_id [15:0] (rr) 8990h writing to this register resets all registers to their default state. reading from this register will indicate device family id 8990h. table 80 chip reset and id saving power at higher supply voltage the avdd supply of the wm8991 can operate between 2.7v and 3.6v. by default, all analogue circuitry on the device is optimized to run at 3.3v. this set-up is also good for all other supply voltages down to 2.7v. at lower voltages, performance can be improved by increasing the bias current. if low power operation is preferred the bias current can be left at the default setting. this is controlled as shown in table 81. register address bit label default description r51 (33h) 8:7 vsel [1:0] 11 anal ogue bias optimisation 00 = reserved 01 = bias current optimized for avdd=2.7v 1x = bias current optimized for avdd=3.3v table 81 bias optimisation
wm8991 production data w pd, december 2008, rev 4.0 134 pop suppression control in normal operation, the analogue circuits in the wm8991 are referenced to vmid (avdd/2). when this reference voltage is first enabled, it will ramp quickly from agnd to avdd/2 and, if connected to an active output, will result in an audible pop being heard. enabling or disabling the output stage after the internal reference has settled can also result in an audible pop as the output rises rapidly from agnd. the wm8991 provides a number of features which enable these pops to be suppressed. the associated control bits are described in this section. careful attention is required to the sequence and timing of these controls in order to get maximum benefit. an outline of some generic control sequences is provided in order to assist users in the definition of application-specific sequences. reference voltages vmid is generated from avdd via a programmable resistor chain as shown in the audio signal paths diagram on page 28. together with the external decoupling capacitor on vmid, the programmable resistor chain results in a slow, normal or fast charging characteristic on vmid. the vmid reference is controlled by vmid_mode[1:0]. the analogue circuits in the wm8991 require a bias current. the default bias current is enabled by setting vref_ena. note that the default bias current source requires vmid to be enabled also. register address bit label default description r1 (01h) 2:1 vmid_mode [1:0] (rw) 00b vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (normal mode) 10 = 2 x 250k divider (standby mode) 11 = 2 x 5k divider (for fast start-up) 0 vref_ena (rw) 0b vref enable (bias for all analogue functions) 0 = vref bias disabled 1 = vref bias enabled table 82 reference voltages soft start control a pop-suppressed start-up requires vmid to be enabled smoothly, without the step change normally associated with the initial stage of the vmid capacitor charging. a pop-suppressed start-up also requires the analogue bias current to be enabled throughout the signal path prior to the vmid reference voltage being applied. the wm8991 incorporates pop-suppression circuits which address these requirements. the wm8991 provides an alternative start-up bias circuit which can be used in place of the default bias current during start-up. the start-up bias current source is enabled by bufdcopen. the start- up bias source is selected (in place of the default bias source) by pobctrl. it is recommended that the start-up bias is used during start-up, before switching back to the higher quality, vref-enabled bias. a soft-start circuit is provided in order to control the switch-on of the vmid reference. the soft-start control circuit is enabled by setting softst. when the soft-start circuit is enabled prior to enabling vmid_mode, the reference voltage rises smoothly, without the step change that would otherwise occur. it is recommended that the soft-start circuit and the output signal path be enabled before vmid is enabled by vmid_mode. soft shut-down of vmid is also provided by the soft-start control circuit and the start-up bias current generator. the soft shut-down of vmid is achieved by setting softst = 1, bufdcopen = 1 and pobctrl = 1 prior to setting vmid_mode = 00.
production data wm8991 w pd, december 2008, rev 4.0 135 the register fields associated with soft start control are described in table 83. register address bit label default description r57 (39h) anti-pop (2) 6 softst 0b enables vmid soft start 0 = disabled 1 = enabled 2 bufdcopen 0b enables the start-up bias current generator 0 = disabled 1 = enabled 1 pobctrl 0b selects the bias current source for output amplifiers and vmid buffer 0 = default bias 1 = start-up bias table 83 soft start control disabled input/output control after start-up, it may be desirable to disable an output stage, in order to reduce power consumption on an unused output. in order to avoid audible pops caused by a disabled output dropping to agnd, the wm8991 can maintain the output at vmid even when the output driver is disabled. this is achieved by connecting a buffered vmid reference to the output. the buffered vmid is enabled by setting bufioen. when bufioen is enabled, it will be connected to any disabled output driver. it is recommended that bufioen is enabled prior to disabling the output driver. the buffered vmid, enabled by bufioen, also maintains the charge on the input capacitors connected to any disabled input amplifier. buffered vmid is connected to each input through 1k resistors. this suppresses the audible artefacts that would otherwise arise when an input amplifier is disabled or enabled. in some applications, a pop generated at an input stage can be entirely suppressed by correctly managing the output stages. however, it may be desirable to use the buffered vmid feature in order to eliminate the input pga start-up delay (the input capacitor charging time) in addition to suppressing any mute/un-mute pops. in applications where frequent enabling and configuration of signal paths is used, it is recommended to enable bufioen at all times. register address bit label default description r57 (39h) anti-pop (2) 3 bufioen 0b enables the buffered vmid reference at disabled inputs/outputs 0 = disabled 1 = enabled table 84 disabled input/output control output discharge control the output paths may also be actively discharged to agnd through internal resistors if desired. this is desirable at start-up in order to achieve a known output stage condition prior to enabling the soft- start vmid reference voltage. this is also desirable in shut-down in order to eliminate pops arising from memory effects in the output capacitors on co mpletion of the controlled shut-down of the vmid reference. note that, for any signal paths that do not use output capacitors (eg. capless headphone drive), the discharge control is not normally required. it is recommended that the output paths should be actively discharged prior to commencing a start- up sequence. the active discharging should then be disabled prior to enabling the output drivers. in shut-down, it is recommended that the output paths should be actively discharged after the vmid reference has settled to agnd and the output drivers have been disabled. the line and headphone output pins are discharged by setting dis_lline, dis_rline, dis_out3, dis_out4, dis_lout and dis_rout, as described in table 85. note that the buffered vmid reference is not applied to an actively discharged output, regardless of bufioen.
wm8991 production data w pd, december 2008, rev 4.0 136 register address bit label default description r56 (38h) anti-pop (1) 5 dis_lline 0b discharges lop and lon outputs via approx 500 resistor 0 = not active 1 = actively discharging lop and lon 4 dis_rline 0b discharges rop and ron outputs via approx 500 resistor 0 = not active 1 = actively discharging rop and ron 3 dis_out3 0b discharges out3 output via approx 500 resistor 0 = not active 1 = actively discharging out3 2 dis_out4 0b discharges out4 output via approx 500 resistor 0 = not active 1 = actively discharging out4 1 dis_lout 0b discharges lout output via approx 500 resistor 0 = not active 1 = actively discharging lout 0 dis_rout 0b discharges rout output via approx 500 resistor 0 = not active 1 = actively discharging rout table 85 output discharge control vmid reference discharge control the vmid reference can be discharged to agnd through internal resistors. discharging vmid ensures that a subsequent start-up procedure commences with a known voltage condition; this is necessary in order to ensure maximum suppression of audible pops associated with start-up. vmid is discharged by setting vmidtog, as described in table 86. register address bit label default description r57 (39h) anti-pop (2) 0 vmidtog 0b connects vmid to ground 0 = disabled 1 = enabled table 86 vmid reference discharge control
production data wm8991 w pd, december 2008, rev 4.0 137 example control sequences pop-suppression control sequences are described below for typical wm8991 operations involving start-up, muting and disabling of signal paths. note that these descriptions are intended for guidance only. application software should be verified and tailored to ensure optimum performance. start-up sequence the following sequence describes the register settings required to enable the headphone outputs lout and rout. it assumes that vmid and vref are initially disabled and actively discharged to agnd. step description register setting 1 discharge output drivers. dis_lout = 1 dis_rout = 1 2 time delay for output capacitors to discharge. 3 enable soft start control and start-up bias source. select start-up bias. softst = 1 bufdcopen = 1 pobctrl = 1 4 disable active discharging of vmid and output drivers. vmidtog = 0 dis_lout = 0 dis_rout = 0 5 enable output drivers. lout_ena = 1 rout_ena = 1 6 enable vmid and vref. vmid_mode = 01 vref_ena = 1 7 time delay for soft-start to execute 8 select default bias source. pobctrl = 0 9 disable soft start control and soft start voltage. softst = 0 bufdcopen = 0 table 87 example start-up control sequence output mute sequence the following sequence describes the register settings required to mute and disable the headphone outputs lout and rout. it assumes that the soft start bias voltage is initially disabled. step description register setting 1 enable buffered vmid at all input and output circuits. bufioen = 1 2 disable output drivers lout_ena = 0 rout_ena = 0 table 88 example mute control sequence output un-mute sequence the following sequence describes the register settings required to enable and un-mute the headphone outputs lout and rout. step description register setting 1 enable output drivers. lout_ena = 1 rout_ena = 1 2 disable buffered vmid at all input and output circuits. bufioen = 0 table 89 example un-mute control sequence
wm8991 production data w pd, december 2008, rev 4.0 138 shut-down and discharge sequence the following sequence describes the register settings required to mute, disable and discharge the headphone outputs lout and rout. it assumes that the soft start control and voltage source is already disabled. step description register setting 1 enable soft start control and start-up bias source. select start-up bias. softst = 1 bufdcopen = 1 pobctrl = 1 2 disable vmid vmid_mode = 00 3 time delay for soft-shutdown to execute 4 disable output drivers. lout_ena = 0 rout_ena = 0 5 discharge output drivers. dis_lout = 1 dis_rout = 1 6 select default bias source. pobctrl = 0 7 disable soft start control and soft start voltage. softst = 0 bufdcopen = 0 table 90 example shut-down and discharge control sequence
production data wm8991 w pd, december 2008, rev 4.0 139 power domains figure 89 wm8991 power domains
wm8991 production data w pd, december 2008, rev 4.0 140 register map dec addrhex addr name 1514131211109876543210 bin default 00 reset 1000_1001_1001_0000 1 1 power management (1) 0 0 0 spk_ena out3_ena out4_ena lout_ena rout_ena 0 0 0 micbias_en a 0 vref_ena 0000_0000_0000_0000 2 2 power management (2) pll_ena tshut_ena tshut_opdi s 0 opclk_ena 0 ainl_ena ainr_ena lin34_ena lin12_ena rin34_ena rin12_ena 0 0 adcl_ena adcr_ena 0110_0000_0000_0000 3 3 power management (3) 0 0 lon_ena lop_ena ron_ena rop_ena 0 spkpga lopga_ena ropga_ena lomix_ena romix_ena 0 0 dacl_ena dacr_ena 0000_0000_0000 _0000 4 4 audio interface (1) aifadcl_sr c aifadcr_sr c aifadc_tdm aifadc_tdm_c han 000 aif_bclk_in v aif_lrclk_i nv 0 0 0 0100_0000_0101_0000 5 5 audio interface (2) dacl_src dacr_src aifdac_tdm aifdac_tdm_c han 0 0 0 0 0 dac_comp dac_compm ode adc_comp adc_compm ode loopback 0100_0000_0000_0000 6 6 clocking (1) toclk_rate toclk_ena 0 0 0 0000_0001_1100_1000 7 7 clocking (2) mclk_src sysclk_src clk_force mclk_inv 0 0 0 0 00p0_0000_0000_0000 8 8 audio interface (3) aif_mstr1 aif_mstr2 aif_sel 0 adclrc_dir 0000_0000_0100_0000 9 9 audio interface (4) alrcgpio1 alrcbgpio6 aif_tris 0 daclrc_dir 0000_0000_0100_0000 10 a dac ctrl 0 0 0 dac_sdmcl k_rate 0 aif_lrclkr ate dac_mono dac_sb_filt dac_muter ate dac_mutem ode 0dac_mute dacl_datin v dacr_datin v 0000_0000_0000_0100 11 b left dac digital volume 0 0 0 0 0 0 0 dac_vu 0000_000p_1100_0000 12 c right dac digital volume 0 0 0 0 0 0 0 dac_vu 0000_000p_1100_0000 13 d digital side tone 0 0 0 0 0000_0000_0000_0000 14 e adc ctrl 0 0 0 0 0 0 0 adc_hpf_en a 0 000 adcl_datin v adcr_datin v 0000_0001_0000_0000 15fleft adc digital volume0000000adc_vu 0000_000p_1100_0000 16 10 right adc digital volume 0 0 0 0 0 0 0 adc_vu 0000_000p_1100_0000 1711 reserved 00000000000000000000_0000_0000_0000 18 12 gpio ctrl 1 0 0 0 irq tempok micshrt micdet pll_lck 0000_pppp_pppp_pppp 19 13 gpio1 & gpio2 gpio2_deb_ ena gpio2_irq_e na gpio2_pu gpio2_pd gpio1_deb_ ena gpio1_irq_e na gpio1_pu gpio1_pd 0001_0000_0000_0000 20 14 gpio3 & gpio4 gpio4_deb_ ena gpio4_irq_e na gpio4_pu gpio4_pd gpio3_deb_ ena gpio3_irq_e na gpio3_pu gpio3_pd 0001_0000_0001_0000 21 15 gpio5 & gpio6 gpio6_deb_ ena gpio6_irq_e na gpio6_pu gpio6_pd gpio5_deb_ ena gpio5_irq_e na gpio5_pu gpio5_pd 0001_0000_0001_0000 22 16 gpioctrl 2 rd_3w_ena mode_3w4w 0 0 tempok_irq _ena micshrt_ir q_ena micdet_irq _ena pll_lck_irq _ena gpi8_deb_e na gpi8_irq_en a 0gpi8_ena gpi7_deb_e na gpi7_irq_en a 0 gpi7_ena 1000_0000_0000_0000 23 17 gpio_pol 0 0 0 irq_inv tempok_po l micshrt_po l micdet_pol pll_lck_po l 0000_1000_0000_0000 24 18 left line input 1&2 volume 0 0 0 0 0 0 0 ipvu[0] li12mute li12zc 0 0000_000p_1000_1011 25 19 left line input 3&4 volume 0 0 0 0 0 0 0 ipvu[1] li34mute li34zc 0 0000_000p_1000_1011 26 1a right line input 1&2 volume 0 0 0 0 0 0 0 ipvu[2] ri12mute ri12zc 0 0000_000p_1000_1011 27 1b right line input 3&4 volume 0 0 0 0 0 0 0 ipvu[3] ri34mute ri34zc 0 0000_000p_1000_1011 28 1c left output volume 0 0 0 0 0 0 0 opvu[0] lozc 0000_000p_0000_0000 29 1d right output volume 0 0 0 0 0 0 0 opvu[1] rozc 0000_000p_0000_0000 30 1e line outputs volume 0 0 0 0 0 0 0 0 0 lonmute lopmute loattn 0 ronmute ropmute roattn 0000_0000_0110_0110 311f out3/4 volume 0000000000out3muteout3attn00out4muteout4attn0000_0000_0010_0010 sw_reset_chip_id[15:0] vmid_mode[1:0] deemp[1:0] mclk_div[1:0] dac_boost[1:0] dac_clkdiv[2:0] adc_clkdiv[2:0] adclrc_rate[10:0] aif_wl[1:0] aif_fmt[1:0] daclrc_rate[10:0] opclkdiv[3:0] bclk_div[3:0] dclkdiv[2:0] gpio4_sel[3:0] gpio6_sel[3:0] dacl_vol[7:0] dacr_vol[7:0] adcl_dac_svol[3:0] adc_hpf_cut[1:0] gpio_status[7:0] gpio2_sel[3:0] gpio1_sel[3:0] adcr_vol[7:0] routvol[6:0] lin12vol[4:0] gpio_pol[7:0] adc_to_dacr[1:0] adc_to_dacl[1:0] adcr_dac_svol[3:0] adcl_vol[7:0] gpio3_sel[3:0] gpio5_sel[3:0] rin12vol[4:0] rin34vol[4:0] lin34vol[4:0] loutvol[6:0]
production data wm8991 w pd, december 2008, rev 4.0 141 dec addrhex addr name 1514131211109876543210 bin default 3220 left opga volume 0000000opvu[2]lopgazc 0000_000p_0111_1001 3321 right opga volume 0000000opvu[3]ropgazc 0000_000p_0111_1001 3422 speaker volume 00000000000000 0000_0000_0000_0011 3523 classd1 0000000cdmode000000110000_0000_0000_0011 3624 classd2 00000000010101010000_0000_0101_0101 3725 classd3 0000000100 0000_0001_0000_0000 3826 classd4 00000000 spkzc 0000_0000_0111_1001 3927 input mixer1 000000000000 0000_0000_0000_0000 4028 input mixer2 00000000lmp4lmn3lmp2lmn1rmp4rmn3rmp2rmn10000_0000_0000_0000 4129 input mixer3 0000000l34mnbl34mnbst0l12mnbl12mnbst0 0000_0000_0000_0000 422a input mixer4 0000000r34mnbr34mnbst0r12mnbr12mnbst0 0000_0000_0000_0000 432b input mixer5 0000000 0000_0000_0000_0000 442c input mixer6 0000000 0000_0000_0000_0000 452d output mixer1 00000000lrblollblolri3lolli3lolr12loll12lo0ldlo0000_0000_0000_0000 462e output mixer2 00000000rlbrorrbrorli3rorri3rorl12rorr12ro0rdro0000_0000_0000_0000 472f output mixer3 0000000 0000_0000_0000_0000 4830 output mixer4 0000000 0000_0000_0000_0000 4931 output mixer5 0000000 0000_0000_0000_0000 5032 output mixer6 0000000 0000_0000_0000_0000 5133 out3/4 mixer 0000000 0li4o3lpgao300ri4o4rpgao40000_0001_1000_0000 5234 line mixer1 000000000llopgalonlropgalonloplon0lr12lopll12lopllopgalop0000_0000_0000_0000 5335 line mixer2 000000000rropgaronrlopgaronropron0rl12roprr12roprropgarop0000_0000_0000_0000 5436 speaker mixer 00000000lb2spkrb2spkli2spkri2spklopgaspkropgaspkldspkrdspk0000_0000_0000_0000 5537 additional control 000000000000000vroi0000_0000_0000_0000 5638 antipop1 0000000000dis_llinedis_rlinedis_out3dis_out4dis_loutdis_rout0000_0000_0000_0000 5739 antipop2 000000000softst00bufioenbufdcopenpobctrlvmidtog0000_0000_0000_0000 583a micbias 00000000 mcd 0 mbsel 0000_0000_0000_0000 593b reserved 00000000000000000000_0000_0000_0000 603c pll1 00000000sdmprescale00 0000_0000_0000_1000 613d pll2 00000000 0000_0000_0011_0001 623e pll3 00000000 0000_0000_0010_0110 11775 access control 00000000000000 ext_access _ena 0 0000_0000_0000_0000 122 7a extended adc control adcl_adcr_ link 0100000000000110010_0000_0000_0011 spkvol[6:0] ropgavol[6:0] spkattn[1:0] lopgavol[6:0] rr12rovol[2:0] ll12lovol[2:0] rl4bvol[2:0] ri2bvol[2:0] li2bvol[2:0] ll4bvol[2:0] lr4bvol[2:0] lli3lovol[2:0] rri3rovol[2:0] rl12rovol[2:0] lr12lovol[2:0] mcdthr[2:0] pllk[15:8] lrblovol[2:0] llblovol[2:0] lri3lovol[2:0] vsel[1:0] rrbrovol[2:0] rlbrovol[2:0] rli3rovol[2:0] rr4bvol[2:0] dcgain[2:0] acgain[2:0] pllk[7:0] ainrmode[1:0] ldbvol[2:0] rdbvol[2:0] plln[3:0] mcdscth[1:0] ainlmode[1:0] note: a bin default value of ?p? indicates a register field where a default value is not applicable e.g. a volume update bit.
wm8991 production data w pd, december 2008, rev 4.0 142 register bits by address register address bit label default description r0 (00h) reset / id 15:0 sw_reset_chip_ id [15:0] (rr) 8990h writing to this register resets all registers to their default state. reading from this register will indicate device family id 8990h. r1 (01h) power management (1) 15:13 000b reserved - do not change 12 spk_ena (rw) 0b spkmix mixer, speaker pga and speaker output enable 0 = disabled 1 = enabled 11 out3_ena (rw) 0b out3 and out3mix enable 0 = disabled 1 = enabled 10 out4_ena (rw) 0b out4 and out4mix enable 0 = disabled 1 = enabled 9 lout_ena (rw) 0b lout (left headphone output) enable 0 = disabled 1 = enabled 8 rout_ena (rw) 0b rout (right headphone output) enable 0 = disabled 1 = enabled 7:5 000b reserved - do not change 4 micbias_ena (rw) 0b micbias enable 0 = off (high impedance output) 1 = on 3 0b reserved - do not change 2:1 vmid_mode [1:0] (rw) 00b vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (normal mode) 10 = 2 x 250k divider (standby mode) 11 = 2 x 5k divider (for fast start-up) 0 vref_ena (rw) 0b vref enable (bias for all analogue functions) 0 = vref bias disabled 1 = vref bias enabled r02 (02h) power management (2) 15 pll_ena (rw) 0b pll enable 0 = disabled 1 = enabled 14 tshut_ena (rw) 1b thermal sensor enable 0 = thermal sensor disabled 1 = thermal sensor enabled 13 tshut_opdis (rw) 1b thermal shutdown enable (requires thermal sensor to be enabled) 0 = thermal shutdown disabled 1 = thermal shutdown enabled 12 0b reserved - do not change 11 opclk_ena (rw) 0b gpio clock output enable 0 = disabled 1 = enabled 10 0b reserved - do not change
production data wm8991 w pd, december 2008, rev 4.0 143 register address bit label default description 9 ainl_ena (rw) 0b left input path enable (enables ainlmux, inmixl, diffinl and rxvoice input to ainlmux) 0 = disabled 1 = enabled 8 ainr_ena (rw) 0b right input path enable (enables ainrmux, inmixr, diffinr and rxvoice input to ainrmux) 0 = disabled 1 = enabled 7 lin34_ena (rw) 0b lin34 input pga enable 0 = disabled 1 = enabled 6 lin12_ena (rw) 0b lin12 input pga enable 0 = disabled 1 = enabled 5 rin34_ena (rw) 0b rin34 input pga enable 0 = disabled 1 = enabled 4 rin12_ena (rw) 0b rin12 input pga enable 0 = disabled 1 = enabled 3:2 00b reserved - do not change 1 adcl_ena (rw) 0b left adc enable 0 = disabled 1 = enabled 0 adcr_ena (rw) 0b right adc enable 0 = disabled 1 = enabled r03 (03h) power management (3) 15:14 00b reserved - do not change 13 lon_ena (rw) 0b lon line out and lonmix enable 0 = disabled 1 = enabled 12 lop_ena (rw) 0b lop line out and lopmix enable 0 = disabled 1 = enabled 11 ron_ena (rw) 0b ron line out and ronmix enable 0 = disabled 1 = enabled 10 rop_ena (rw) 0b rop line out and ropmix enable 0 = disabled 1 = enabled 9 0b reserved - do not change 8 spkpga_ena (rw) 0b spkmix mixer and speaker pga enable 0 = disabled 1 = enabled note that spkmix and spkpga are also enabled when spk_ena is set. 7 lopga_ena (rw) 0b lopga left volume control enable 0 = disabled 1 = enabled 6 ropga_ena (rw) 0b ropga right volume control enable 0 = disabled 1 = enabled
wm8991 production data w pd, december 2008, rev 4.0 144 register address bit label default description 5 lomix_ena (rw) 0b lomix left output mixer enable 0 = disabled 1 = enabled 4 romix_ena (rw) 0b romix right output mixer enable 0 = disabled 1 = enabled 3:2 00b reserved - do not change 1 dacl_ena (rw) 0b left dac enable 0 = disabled 1 = enabled 0 dacr_ena (rw) 0b right dac enable 0 = disabled 1 = enabled r04 (04h) audio interface (1) 15 aifadcl_src 0b left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 14 aifadcr_src 1b right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 13 aifadc_tdm 0b adc tdm enable 0 = normal adcdat operation 1 = tdm enabled on adcdat 12 aifadc_tdm_ chan 0b adcdat tdm channel select 0 = adcdat outputs data on slot 0 1 = adcdat output data on slot 1 11:9 0b reserved - do not change 8 aif_bclk_inv 0b bclk invert 0 = bclk not inverted 1 = bclk inverted 7 aif_lrclk_inv 0b right, left and i 2 s modes ? lrclk polarity 0 = normal lrclk polarity 1 = invert lrclk polarity dsp mode ? mode a/b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 6:5 aif_wl [1:0] 10b digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 4:3 aif_fmt [1:0] 10b digital audio interface format 00 = right justified 01 = left justified 10 = i 2 s format 11 = dsp mode 2:0 0b reserved - do not change r05 (05h) audio interface (2) 15 dacl_src 0b left dac data source select 0 = left dac outputs left channel data 1 = left dac outputs right channel data 14 dacr_src 1b right dac data source select 0 = right dac outputs left channel data 1 = right dac outputs right channel data
production data wm8991 w pd, december 2008, rev 4.0 145 register address bit label default description 13 aifdac_tdm 0b dac tdm enable 0 = normal dacdat operation 1 = tdm enabled on dacdat 12 aifdac_tdm_ chan 0b dacdat tdm channel select 0 = dacdat data input on slot 0 1 = dacdat data input on slot 1 11:10 dac_boost [1:0] 00b dac input volume boost 00 = 0db 01 = +6db (input data must not exceed -6dbfs) 10 = +12db (input data must not exceed -12dbfs) 11 = +18db (input data must not exceed -18dbfs) 9:5 reserved - do not change 4 dac_comp 0b dac companding enable 0 = disabled 1 = enabled 3 dac_compmode 0b dac companding type 0 = -law 1 = a-law 2 adc_comp 0b adc companding enable 0 = disabled 1 = enabled 1 adc_compmode 0b adc companding type 0 = -law 1 = a-law 0 loopback 0b digital loopback function 0 = no loopback 1 = loopback enabled (adc data output is directly input to dac data input). note: adc and dac left/right clocks must be set to the same pin when using loo pback function (alrcgpio1=1) r06 (06h) clocking (1) 15 toclk_rate 0b timeout clock rate (selects clock to be used for volume update timeout and gpio input de-bounce) 0 = sysclk / 2 21 (slower response) 1 = sysclk / 2 19 (faster response) 14 toclk_ena 0b timeout clock enable (this clock is required for volume update timeout and gpio input de-bounce) 0 = disabled 1 = enabled 13 reserved - do not change 12:9 opclkdiv [3:0] 0000b gpio output clock divider 0000 = sysclk 0001 = sysclk / 2 0010 = sysclk / 3 0011 = sysclk / 4 0100 = sysclk / 5.5 0101 = sysclk / 6 0110 = sysclk / 8 0111 = sysclk / 12 1000 = sysclk / 16 1001 to 1111 = reserved
wm8991 production data w pd, december 2008, rev 4.0 146 register address bit label default description 8:6 dclkdiv [2:0] 111b class d clock divider 000 = sysclk 001 = sysclk / 2 010 = sysclk / 3 011 = sysclk / 4 100 = sysclk / 6 101 = sysclk / 8 110 = sysclk / 12 111 = sysclk / 16 5 0b reserved - do not change 4:1 bclk_div [3:0] 0100b bclk frequency (master mode) 0000 = sysclk 0001 = sysclk / 1.5 0010 = sysclk / 2 0011 = sysclk / 3 0100 = sysclk / 4 0101 = sysclk / 5.5 0110 = sysclk / 6 0111 = sysclk / 8 1000 = sysclk / 11 1001 = sysclk / 12 1010 = sysclk / 16 1011 = sysclk / 22 1100 = sysclk / 24 1101 = sysclk / 32 1110 = sysclk / 44 1111 = syscl:k / 48 0 0b reserved - do not change r07 (07h) clocking (2) 15 mclk_src 0b mclk source select 0 = mclk pin 1 = gpio2/mclk2 pin 14 sysclk_src 0b sysclk source select 0 = mclk (or mclk2 if mclk_src=1) 1 = pll output 13 clk_force 0b forces clock source selection 0 = existing sysclk source (mclk, mclk2 or pll output) must be active when changing to a new clock source. 1 = allows existing mclk source to be disabled before changing to a new clock source. 12:11 mclk_div [1:0] 00b sysclk pre-divider. clock source (mclk, mclk2 or pll output) will be divided by this value to generate sysclk. 00 = divide sysclk by 1 01 = reserved 10 = divide sysclk by 2 11 = reserved 10 mclk_inv 0b mclk invert 0 = master clock (mclk or mclk2) not inverted 1 = master clock (mclk or mclk2) inverted 9:8 00b reserved - do not change
production data wm8991 w pd, december 2008, rev 4.0 147 register address bit label default description 7:5 adc_clkdiv [2:0] 000b adc sample rate divider 000 = sysclk / 1.0 001 = sysclk / 1.5 010 = sysclk / 2.0 011 = sysclk / 3.0 100 = sysclk / 4.0 101 = sysclk / 5.5 110 = sysclk / 6.0 111= reserved 4:2 dac_clkdiv [2:0] 000b dac sample rate divider 000 = sysclk / 1.0 001 = sysclk / 1.5 010 = sysclk / 2.0 011 = sysclk / 3.0 100 = sysclk / 4.0 101 = sysclk / 5.5 110 = sysclk / 6.0 111= reserved 1:0 00b reserved - do not change r08 (08h) audio interface (3) 15 aif_mstr1 0b audio interface 1 master mode select 0 = slave mode 1 = master mode 14 aif_mstr2 0b audio interface 2 master mode select 0 = slave mode 1 = master mode 13 aif_sel 0b audio interface select 0 = audio interface 1 1 = audio interface 2 (gpio3/bclk2, gpio4/daclrc2, gpio5/dacdat2) 12 0b reserved - do not change 11 adclrc_dir 0b adclrc direction (forces adclrc clock to be output in slave mode) 0 = adclrc normal operation 1 = adclrc clock output enabled 10:0 adclrc_rate [10:0] 040h adclrc rate adclrc clock output = bclk / adclrc_rate integer (lsb = 1) valid from 8..2047 r09 (09h) audio interface (4) 15 alrcgpio1 0b adclrc/gpio1 pin function select 0 = adclrc pin 1 = gpio1 pin (adclrc connected to daclrc internally) 14 alrcbgpio6 0b gpio6/adclrcb pin function select 0 = gpio6 pin 1 = inverted adclrc clock output 13 aif_tris 0b audio interface and gpio tristate 0 = audio interface and gpio pins operate normally 1 = tristate all audio interface and gpio pins 12 0b reserved - do not change 11 daclrc_dir 0b daclrc direction (forces daclrc clock to be output in slave mode) 0 = daclrc normal operation 1 = daclrc clock output enabled
wm8991 production data w pd, december 2008, rev 4.0 148 register address bit label default description 10:0 daclrc_rate [10:0] 040h daclrc rate daclrc clock output = bclk / daclrc_rate integer (lsb = 1) valid from 8..2047 r10 (0ah) dac control 15:13 000b reserved - do not change 12 dac_sdmclk_ rate 0b dac clocking rate 0 = normal operation (64fs) 1 = sysclk/4 11 0b reserved - do not change 10 aif_lrclkrate 0b lrclk rate 0 = normal mode (256 * fs) 1 = usb mode (272 * fs) 9 dac_mono 0b dac mono mix 0 = stereo 1 = mono (mono mix output on enabled dacs) 8 dac_sb_filt 0b selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode 7 dac_muterate 0b dac soft mute ramp rate 0 = fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) 6 dac_mutemode 0b dac soft mute mode 0 = disabling soft-mute (dac_mute=0) will cause the dac volume to change immediately to dacl_vol and dacr_vol settings 1 = disabling soft-mute (dac_mute=0) will cause the dac volume to ramp up gradually to the dacl_vol and dacr_vol settings 5:4 deemp 00b dac de-emphasis control 00 = de-emphasis disabled 01 = de-emphasis enabled (optimised for fs=32khz) 10 = de-emphasis enabled (optimised for fs=44.1khz) 11 = de-emphasis enabled (optimised for fs=48khz) 3 0b reserved - do not change 2 dac_mute 1b dac soft mute control 0 = dac un-mute 1 = dac mute 1 dacl_datinv 0b left dac invert 0 = left dac output not inverted 1 = left dac output inverted 0 dacr_datinv 0b right dac invert 0 = right dac output not inverted 1 = right dac output inverted r11 (0bh) left dac digital volume 15:9 00h reserved - do not change 8 dac_vu n/a dac volume update writing a 1 to this bit will cause left and right dac volume to be updated simultaneously 7:0 dacl_vol [7:0] 1100_000 0b (0db) left dac digital volume (see table 26 for volume settings) r12 (0ch) 15:9 00h reserved - do not change
production data wm8991 w pd, december 2008, rev 4.0 149 register address bit label default description right dac digital volume 8 dac_vu n/a dac volume update writing a 1 to this bit will cause left and right dac volume to be updated simultaneously 7:0 dacr_vol [7:0] 1100_ 0000b (0db) right dac digital volume (see table 26 for volume settings) r13 (0dh) digital sidetone 15:13 000b reserved - do not change 12:9 adcl_dac_svol [3:0] 0000b left channel digital sidetone volume (see table 23 for volume range) 8:5 adcr_dac_svol [3:0] 0000b right channel digital sidetone volume (see table 23 for volume range) 4 0b reserved - do not change 3:2 adc_to_dacl [1:0] 00b left dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved 1:0 adc_to_dacr [1:0] 00b right dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved r14 (0eh) adc control 15:9 00h reserved - do not change 8 adc_hpf_ena 1b adc digital high pass filter enable 0 = disabled 1 = enabled 7 0b reserved - do not change 6:5 adc_hpf_cut [1:0] 00b adc digital high pass filter cut-off frequency (fc) 00 = hi-fi mode (fc=4hz at fs=48khz) 01 = voice mode 1 (fc=127hz at fs=16khz) 10 = voice mode 2 (fc=130hz at fs=8khz) 11 = voice mode 3 (fc=267hz at fs=8khz) (note: fc scales with sample rate. see table 18 for cut-off frequencies at all supported sample rates) 4:2 000b reserved - do not change 1 adcl_datinv 0b left adc invert 0 = left adc output not inverted 1 = left adc output inverted 0 adcr_datinv 0b right adc invert 0 = right adc output not inverted 1 = right adc output inverted r15 (0fh) left adc digital volume 15:9 00h reserved - do not change 8 adc_vu n/a adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 7:0 adcl_vol [7:0] 1100_ 0000b (0db) left adc digital volume (see table 16 for volume range) r16 (10h) right adc digital volume 15:9 00h reserved - do not change 8 adc_vu n/a adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously
wm8991 production data w pd, december 2008, rev 4.0 150 register address bit label default description 7:0 adcr_vol [7:0] 1100_ 0000b (0db) right adc digital volume (see table 16 for volume range) r17 (11h) 15:0 0000h reserved - do not change r18 (12h) gpio control (1) 15:13 0db reserved - do not change 12 irq (ro) read only irq readback (allows polling of irq status) 11 tempok (rr) read or reset temperature ok status read- 0 = device temperature not ok 1 = device temperature ok write - 1 = reset tempok latch 10 micshrt (rr) read or reset micbias short status read- 0 = micbias ok 1 = micbias shorted write- 1 = reset micshrt latch 9 micdet (rr) read or reset micbias detect status micbias microphone detect readback read- 0 = no microphone detected 1 = microphone detected write- 1 = reset micdet latch 8 pll_lck (rr) read or reset pll lock status read- 0 = pll not locked 1 = pll locked write- 1 = reset pll_lck latch 7:0 gpio_status [7:0] (rr) read or reset gpio and gpi input pin status gpio_status[7] = gpi8 pin status gpio_status[6] = gpi7 pin status gpio_status[5] = gpio6 pin status gpio_status[4] = gpio5 pin status gpio_status[3] = gpio4 pin status gpio_status[2] = gpio3 pin status gpio_status[1] = gpio2 pin status gpio_status[0] = gpio1 pin status r19 (13h) gpio1 and gpio2 15 gpio2_deb_ena 0b gpio2 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 14 gpio2_irq_ena 0b gpio2 irq enable 0 = disabled 1 = enabled (gpio2 input will generate irq) 13 gpio2_pu 0b gpio2 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ) 12 gpio2_pd 1b gpio2 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k )
production data wm8991 w pd, december 2008, rev 4.0 151 register address bit label default description 11:8 gpio2_sel [3:0] 0000b gpio2 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved 7 gpio1_deb_ena 0b gpio1 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 6 gpio1_irq_ena 0b gpio1 irq enable 0 = disabled 1 = enabled (gpio1 input will generate irq) 5 gpio1_pu 0b gpio1 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ) 4 gpio1_pd 0b gpio1 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k ) 3:0 gpio1_sel [3:0] 0000b gpio1 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved r20 (14h) gpio3 and gpio4 15 gpio4_deb_ena 0b gpio4 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 14 gpio4_irq_ena 0b gpio4 irq enable 0 = disabled 1 = enabled (gpio4 input will generate irq) 13 gpio4_pu 0b gpio4 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ) 12 gpio4_pd 1b gpio4 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k )
wm8991 production data w pd, december 2008, rev 4.0 152 register address bit label default description 11:8 gpio4_sel [3:0] 0000b gpio4 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved 7 gpio3_deb_ena 0b gpio3 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 6 gpio3_irq_ena 0b gpio3 irq enable 0 = disabled 1 = enabled (gpio3 input will generate irq) 5 gpio3_pu 0b gpio3 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ) 4 gpio3_pd 1b gpio3 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k ) 3:0 gpio3_sel [3:0] 0000b gpio3 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved r21 (15h) gpio5 and gpio6 15 gpio6_deb_ena 0b gpio6 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 14 gpio6_irq_ena 0b gpio6 irq enable 0 = disabled 1 = enabled (gpio6 input will generate irq) 13 gpio6_pu 0b gpio6 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ) 12 gpio6_pd 1b gpio6 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k )
production data wm8991 w pd, december 2008, rev 4.0 153 register address bit label default description 11:8 gpio6_sel [3:0] 0000b gpio6 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved 7 gpio5_deb_ena 0b gpio5 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 6 gpio5_irq_ena 0b gpio5 irq enable 0 = disabled 1 = enabled (gpio5 input will generate irq) 5 gpio5_pu 0b gpio5 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled (approx 150k ) 4 gpio5_pd 1b gpio5 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled (approx 150k ) 3:0 gpio5_sel [3:0] 0000b gpio5 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = pll lock output 0101 = temperature ok output 0110 = sdout data output 0111 = irq output 1000 = mic detect 1001 = mic short circuit detect 1010 to 1111 = reserved r22 (16h) gpi7 and gpi8 15 rd_3w_ena 1b 3- / 4-wire readback configuration 1 = 3-wire mode 0 = 4-wire mode, using gpio pin 14 mode_3w4w 0b 3-wire mode 0 = push 0/1 1 = open-drain 4-wire mode 0 = push 0/1 1 = wired-or 13:12 00b reserved - do not change 11 tempok_irq_ena 0b temperature sensor irq enable 0 = disabled 1 = enabled 10 micshrt_irq_ ena 0b micbias short circuit detect irq enable 0 = disabled 1 = enabled
wm8991 production data w pd, december 2008, rev 4.0 154 register address bit label default description 9 micdet_irq_ena 0b micbias current detect irq enable 0 = disabled 1 = enabled 8 pll_lck_irq_ena 0b pll lock irq enable 0 = disabled 1 = enabled 7 gpi8_deb_ena 0b gpi8 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 6 gpi8_irq_ena 0b gpi8 irq enable 0 = disabled 1 = enabled (gpi8 input will generate irq) 5 0b reserved - do not change 4 gpi8_ena 0b gpi8 input pin enable 0 = rin3/gpi8 pin disabled as gpi8 input 1 = rin3/gpi8 pin enabled as gpi8 input 3 gpi7_deb_ena 0b gpi7 input de-bounce 0 = disabled (not de-bounced) 1 = enabled (requires mclk input and toclk_ena=1) 2 gpi7_irq_ena 0b gpi7 irq enable 0 = disabled 1 = enabled (gpi7 input will generate irq) 1 0b reserved - do not change 0 gpi7_ena 0b gpi7 input pin enable 0 = lin3/gpi7 pin disabled as gpi7 input 1 = lin3/gpi7 pin enabled as gpi7 input r23 (17h) gpio control (2) 15:13 0000b reserved - do not change 12 irq_inv (rw) 0b irq invert 0 = irq output active high 1 = irq output active low 11 tempok_pol (rw) 1b temperature sensor polarity 0 = non-inverted 1 = inverted 10 micshrt_pol (rw) 0b micbias short circuit detect polarity 0 = non-inverted 1 = inverted 9 micdet_pol (rw) 0b micbias current detect polarity 0 = non-inverted 1 = inverted 8 pll_lck_pol (rw) 0b pll lock polarity 0 = non-inverted 1 = inverted 7:0 gpio_pol[7:0] (rw) 00h gpion input polarity 0 = non-inverted 1 = inverted gpio_pol[7]: gpi8 polarity gpio_pol[6]: gpi7 polarity gpio_pol[5]: gpio6 polarity gpio_pol[4]: gpio5 polarity gpio_pol[3]: gpio4 polarity gpio_pol[2]: gpio3 polarity gpio_pol[1]: gpio2 polarity gpio_pol[0]: gpio1 polarity r24 (18h) 15:9 00h reserved - do not change
production data wm8991 w pd, december 2008, rev 4.0 155 register address bit label default description lin12 input pga volume 8 ipvu[0] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 li12mute 1b lin12 pga mute 0 = disable mute 1 = enable mute 6 li12zc 0b lin12 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 5 0b reserved - do not change 4:0 lin12vol [4:0] 01011b lin12 volume (see table 6 for pga volume range) r25 (19h) lin34 input pga volume 15:9 00h reserved - do not change 8 ipvu[1] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 li34mute 1b lin34 pga mute 0 = disable mute 1 = enable mute 6 li34zc 0b lin34 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 5 0b reserved - do not change 4:0 lin34vol [4:0] 01011b lin34 volume (see table 6 for pga volume range) r26 (1ah) rin12 input pga volume 15:9 00h reserved - do not change 8 ipvu[2] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 ri12mute 1b rin12 pga mute 0 = disable mute 1 = enable mute 6 ri12zc 0b rin12 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 5 0b reserved - do not change 4:0 rin12vol [4:0] 01011b rin12 volume (see table 6 for pga volume range) r27 (1bh) rin34 input pga volume 15:9 00h reserved - do not change 8 ipvu[3] n/a input pga volume update writing a 1 to this bit will cause all input pga volumes to be updated simultaneously (lin12, lin34, rin12 and rin34) 7 ri34mute 1b rin34 pga mute 0 = disable mute 1 = enable mute 6 ri34zc 0b rin34 pga zero cross detector 0 = change gain immediately 1 = change gain on zero cross only 5 0b reserved - do not change 4:0 rin34vol [4:0] 01011b rin34 volume (see table 6 for pga volume range)
wm8991 production data w pd, december 2008, rev 4.0 156 register address bit label default description r28 (1ch) left headphone output volume 15:9 00h reserved - do not change 8 opvu[0] n/a output pga volume update writing a 1 to this bit will update lopga, ropga, loutvol and routvol volumes simultaneously. 7 lozc 0b left headphone output zero cross enable 0 = zero cross disabled 1 = zero cross enabled 6:0 loutvol [6:0] 00h (mute) left headphone output volume (see table 36 for output pga volume control range) r29 (1dh) right headphone output volume 15:9 00h reserved - do not change 8 opvu[1] n/a output pga volume update writing a 1 to this bit will update lopga, ropga, loutvol and routvol volumes simultaneously. 7 rozc 0b right headphone output zero cross enable 0 = zero cross disabled 1 = zero cross enabled 6:0 routvol [6:0] 00h (mute) right headphone output volume (see table 36 for output pga volume control range) r30 (1eh) line output volume 15:7 000h reserved - do not change 6 lonmute 1b lon line output mute 0 = un-mute 1 = mute 5 lopmute 1b lop line output mute 0 = un-mute 1 = mute 4 loattn 0b lop attenuation 0 = 0db 1 = -6db 3 0b reserved - do not change 2 ronmute 1b ron line output mute 0 = un-mute 1 = mute 1 ropmute 1b rop line output mute 0 = un-mute 1 = mute 0 roattn 0b rop attenuation 0 = 0db 1 = -6db r31 (1fh) out3 and out4 volume 15:6 00000000 00b reserved - do not change 5 out3mute 1b out3 mute 0 = un-mute 1 = mute 4 out3attn 0b out3 attenuation 0 = 0db 1 = -6db 3:2 00b reserved - do not change 1 out4mute 1b out4 mute 0 = un-mute 1 = mute 0 out4attn 0b out4 attenuation 0 = 0db 1 = -6db r32 (20h) 15:9 00h reserved - do not change
production data wm8991 w pd, december 2008, rev 4.0 157 register address bit label default description lopga volume 8 opvu[2] n/a output pga volume update writing a 1 to this bit will update lopga, ropga, loutvol and routvol volumes simultaneously. 7 lopgazc 0b lopga zero cross enable 0 = zero cross disabled 1 = zero cross enabled 6:0 lopgavol [6:0] 79h (0db) lopga volume (see table 36 for output pga volume control range) r33 (21h) ropga volume 15:9 00h reserved - do not change 8 opvu[3] n/a output pga volume update writing a 1 to this bit will update lopga, ropga, loutvol and routvol volumes simultaneously. 7 ropgazc 0b ropga zero cross enable 0 = zero cross disabled 1 = zero cross enabled 6:0 ropgavol [6:0] 79h (0db) ropga volume (see table 36 for output pga volume control range) r34 (22h) speaker volume 15:2 0000h reserved - do not change 1:0 spkattn [1:0] 11b speaker output attenuation ( spkn and s pkp) 00 = 0db 01 = -6db 10 = -12db 11 = mute r35 (23h) class d (1) 15:9 00h reserved - do not change 8 cdmode 0b speaker class d mode enable 0 = class d mode 1 = class ab mode 7:0 00000011 b reserved - do not change r36 (24h) class d (2) 15:0 0055h reserved - do not change r37 (25h) class d (3) 15:6 00000001 00b reserved - do not change 5:3 dcgain [2:0] 000b dc speaker boost 000 = 1.00x boost (+0db) 001 = 1.27x boost (+2.1db) 010 = 1.40x boost (+2.9db) 011 = 1.52x boost (+3.6db) 100 = 1.67x boost (+4.5db) 101 = 1.8x boost (+5.1db) 110 to 111 = reserved 2:0 acgain [2:0] 000b ac speaker boost 000 = 1.00x boost (+0db) 001 = 1.27x boost (+2.1db) 010 = 1.40x boost (+2.9db) 011 = 1.52x boost (+3.6db) 100 = 1.67x boost (+4.5db) 101 = 1.8x boost (+5.1db) 110 to 111 = reserved r38 (26h) class d (4) 15:8 00h reserved - do not change 7 spkzc 0b spkpga zero cross e nable 0 = zero cross disabled 1 = zero cross enabled
wm8991 production data w pd, december 2008, rev 4.0 158 register address bit label default description 6:0 spkvol [6:0] 79h (0db) spkpga volume (see table 36 for spkpga volume control r ange) r39 (27h) input mixers (1) 15:4 000h reserved - do not change 3:2 ainlmode [1:0] 00b ainlmux input source 00 = inmixl (left input mixer) 01 = rxvoice (rxp - rxn) 10 = diffinl (lin12 pga - lin34 pga) 11 = (reserved) 1:0 ainrmode [1:0] 00b ainrmux input source 00 = inmixr (right input mixer) 01 = rxvoice (rxp - rxn) 10 = diffinr (rin12 pga - rin34 pga) 11 = (reserved) r40 (28h) input mixers (2) 15:8 00h reserved - do not change 7 lmp4 0b lin34 pga non-inverting input select 0 = lin4 not connected to pga 1 = lin4 connected to pga 6 lmn3 0b lin34 pga inverting input select 0 = lin3 not connected to pga 1 = lin3 connected to pga 5 lmp2 0b lin12 pga non-inverting input select 0 = lin2 not connected to pga 1 = lin2 connected to pga 4 lmn1 0b lin12 pga inverting input select 0 = lin1 not connected to pga 1 = lin1 connected to pga 3 rmp4 0b rin34 pga non-inverting input select 0 = rin4 not connected to pga 1 = rin4 connected to pga 2 rmn3 0b rin34 pga inverting input select 0 = rin3 not connected to pga 1 = rin3 connected to pga 1 rmp2 0b rin12 pga non-inverting input select 0 = rin2 not connected to pga 1 = rin2 connected to pga 0 rmn1 0b rin12 pga inverting input select 0 = rin1 not connected to pga 1 = rin1 connected to pga r41 (29h) input mixers (3) 15:9 00h reserved - do not change 8 l34mnb 0b lin34 pga output to inmixl mute 0 = mute 1 = un-mute 7 l34mnbst 0b lin34 pga output to inmixl gain 0 = 0db 1 = +30db 6 0b reserved - do not change 5 l12mnb 0b lin12 pga output to inmixl mute 0 = mute 1 = un-mute 4 l12mnbst 0b lin12 pga output to inmixl gain 0 = 0db 1 = +30db 3 0b reserved - do not change
production data wm8991 w pd, december 2008, rev 4.0 159 register address bit label default description 2:0 ldbvol [2:0] 000b lomix to inmixl gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r42 (2ah) input mixers (4) 15:9 00h reserved - do not change 8 r34mnb 0b rin34 pga output to inmixr mute 0 = mute 1 = un-mute 7 r34mnbst 0b rin34 pga output to inmixr gain 0 = 0db 1 = +30db 6 0b reserved - do not change 5 r12mnb 0b rin12 pga output to inmixr mute 0 = mute 1 = un-mute 4 r12mnbst 0b rin12 pga output to inmixr gain 0 = 0db 1 = +30db 3 0b reserved - do not change 2:0 rdbvol [2:0] 000b romix to inmixr gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r43 (2bh) input mixers (5) 15:9 00h reserved - do not change 8:6 li2bvol [2:0] 000b lin2 pin to inmixl gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 5:3 lr4bvol [2:0] 000b rxvoice to ainlmux gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db
wm8991 production data w pd, december 2008, rev 4.0 160 register address bit label default description 2:0 ll4bvol [2:0] 000b lin4/rxn pin to inmixl gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r44 (2ch) input mixers (6) 15:9 00h reserved - do not change 8:6 ri2bvol [2:0] 000b rin2 pin to inmixr gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 5:3 rl4bvol [2:0] 000b rxvoice to ainrmux gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db 2:0 rr4bvol [2:0] 000b rin4/rxp pin to inmixr gain and mute 000 = mute 001 = -12db 010 = -9db 011 = -6db 100 = -3db 101 = 0db 110 = +3db 111 = +6db r45 (2dh) output mixers (1) 15:8 00h reserved - do not change 7 lrblo 0b ainrmux output (right adc bypass) to lomix mute 0 = mute 1 = un-mute 6 llblo 0b ainlmux output (left adc bypass) to lomix mute 0 = mute 1 = un-mute 5 lri3lo 0b rin3 to lomix mute 0 = mute 1 = un-mute 4 lli3lo 0b lin3 to lomix mute 0 = mute 1 = un-mute 3 lr12lo 0b rin12 pga output to lomix mute 0 = mute 1 = un-mute
production data wm8991 w pd, december 2008, rev 4.0 161 register address bit label default description 2 ll12lo 0b lin12 pga output to lomix mute 0 = mute 1 = un-mute 1 0b reserved - do not change 0 ldlo 0b left dac to lomix mute 0 = mute 1 = un-mute note: ldlo must be muted when ld spk=1 r46 (2eh) output mixers (2) 15:8 00h reserved - do not change 7 rlbro 0b ainlmux output (left adc bypass) to romix mute 0 = mute 1 = un-mute 6 rrbro 0b ainrmux output (right adc bypass) to romix 0 = mute 1 = un-mute 5 rli3ro 0b lin3 to romix mute 0 = mute 1 = un-mute 4 rri3ro 0b rin3 to romix mute 0 = mute 1 = un-mute 3 rl12ro 0b lin12 pga output to romix mute 0 = mute 1 = un-mute 2 rr12ro 0b rin12 pga output to romix mute 0 = mute 1 = un-mute 1 0b reserved - do not change 0 rdro 0b right dac to romix mute 0 = mute 1 = un-mute note: rdro must be muted when rd spk=1 r47 (2fh) output mixers (3) 15:9 00h reserved - do not change 8:6 lli3lovol [2:0] 000b lin3 pin to lomix volume (see table 34 for volume range) 5:3 lr12lovol [2:0] 000b rin12 pga output to lomix volume (see table 34 for volume range) 2:0 ll12lovol [2:0] 000b lin12 pga output to lomix volume (see table 34 for volume range) r48 (30h) output mixers (4) 15:9 00h reserved - do not change 8:6 rri3rovol [2:0] 000b rin3 to romix volume (see table 34 for volume range) 5:3 rl12rovol [2:0] 000b lin12 pga output to romix volume (see table 34 for volume range) 2:0 rr12rovol [2:0] 000b rin12 pga output to romix volume (see table 34 for volume range) r49 (31h) output mixers (5) 15:9 000h reserved - do not change 8:6 lri3lovol [2:0] 000b rin3 to lomix volume (see table 34 for volume range) 5:3 lrblovol [2:0] 000b ainrmux output (right adc bypass) to lomix volume (see table 34 for volume range) 2:0 llblovol [2:0] 000b ainlmux output (left adc bypass) to lomix volume (see table 34 for volume range) r50 (32h) 15:9 00h reserved - do not change
wm8991 production data w pd, december 2008, rev 4.0 162 register address bit label default description output mixers (6) 8:6 rli3rovol [2:0] 000b lin3 to romix volume (see table 34 for volume range) 5:3 rlbrovol [2:0] 000b ainlmux output (left adc bypass) to romix volume (see table 34 for volume range) 2:0 rrbrovol [2:0] 000b ainrmux output (right adc bypass) to romix volume (see table 34 for volume range) r51 (33h) out3 and out4 mixers 15:9 00h reserved - do not change 8:7 vsel [1:0] 11b analogue bias optimisation 00 = reserved 01 = bias current optimized for avdd=2.7v 1x = lowest bias current, optimized for avdd=3.3v 6 0b reserved - do not change 5 li4o3 0b lin4/rxn pin to out3mix 0 = mute 1 = un-mute 4 lpgao3 0b lopga to out3mix 0 = mute 1 = un-mute 3:2 00b reserved - do not change 1 ri4o4 0b rin4/rxp pin to out4mix 0 = mute 1 = un-mute 0 rpgao4 0b ropga to out4mix 0 = mute 1 = un-mute r52 (34h) line output mixers (1) 15:7 000h reserved - do not change 6 llopgalon 0b lopga to lonmix 0 = mute 1 = un-mute 5 lropgalon 0b ropga to lonmix 0 = mute 1 = un-mute 4 loplon 0b inverted lop output to lonmix 0 = mute 1 = un-mute 3 0b reserved - do not change 2 lr12lop 0b rin12 pga output to lopmix 0 = mute 1 = un-mute 1 ll12lop 0b lin12 pga output to lopmix 0 = mute 1 = un-mute 0 llopgalop 0b lopga to lopmix 0 = mute 1 = un-mute r53 (35h) line output mixers (2) 15:7 000h reserved - do not change 6 rropgaron 0b ropga to ronmix 0 = mute 1 = un-mute 5 rlopgaron 0b lopga to ronmix 0 = mute 1 = un-mute
production data wm8991 w pd, december 2008, rev 4.0 163 register address bit label default description 4 ropron 0b inverted rop output to ronmix 0 = mute 1 = un-mute 3 0b reserved - do not change 2 rl12rop 0b lin12 pga output to ropmix 0 = mute 1 = un-mute 1 rr12rop 0b rin12 pga output to ropmix 0 = mute 1 = un-mute 0 rropgarop 0b ropga to ropmix 0 = mute 1 = un-mute r54 (36h) speaker output mixer 15:8 000h reserved - do not change 7 lb2spk 0b ainlmux output to spkmix 0 = mute 1 = un-mute 6 rb2spk 0b ainrmux output to spkmix 0 = mute 1 = un-mute 5 li2spk 0b lin2 to spkmix 0 = mute 1 = un-mute 4 ri2spk 0b rin2 to spkmix 0 = mute 1 = un-mute 3 lopgaspk 0b lopga to spkmix 0 = mute 1 = un-mute 2 ropgaspk 0b ropga to spkmix 0 = mute 1 = un-mute 1 ldspk 0b left dac to spkmix 0 = mute 1 = un-mute note: ldspk must be muted w hen ldlo=1 0 rdspk 0b right dac to spkmix 0 = mute 1 = un-mute note: rdspk must be muted w hen rdro=1 r55 (37h) additional control 15:1 0000h reserved - do not change 0 vroi 0b vref to analogue output resistance (disabled outputs) 0 = 20k (headphone) or 10k (line out) from buffered vmid to output 1 = 500 from buffered vmid to output r56 (38h) anti-pop (1) 15:6 000h reserved - do not change 5 dis_lline 0b discharges lop and lon outputs via approx 500 resistor 0 = not active 1 = actively discharging lop and lon 4 dis_rline 0b discharges rop and ron outputs via approx 500 resistor 0 = not active 1 = actively discharging rop and ron
wm8991 production data w pd, december 2008, rev 4.0 164 register address bit label default description 3 dis_out3 0b discharges out3 output via approx 500 resistor 0 = not active 1 = actively discharging out3 2 dis_out4 0b discharges out4 output via approx 500 resistor 0 = not active 1 = actively discharging out4 1 dis_lout 0b discharges lout output via approx 500 resistor 0 = not active 1 = actively discharging lout 0 dis_rout 0b discharges rout output via approx 500 resistor 0 = not active 1 = actively discharging rout r57 (39h) anti-pop (2) 15:7 0000_000 0_0b reserved - do not change 6 softst 0b enables vmid soft start 0 = disabled 1 = enabled 5:4 00b reserved - do not change 3 bufioen 0b enables the vgs / r current generator and the analogue input and output bias 0 = disabled 1 = enabled 2 bufdcopen 0b enables the vgs / r current generator 0 = disabled 1 = enabled 1 pobctrl 0b selects the bias current source for output amplifiers and vmid buffer 0 = vmid / r bias 1 = vgs / r bias 0 vmidtog 0b connects vmid to ground 0 = disabled 1 = enabled r58 (3ah) microphone bias 15:8 0000_000 0b reserved - do not change 7:6 mcdscth [1:0] 00b micbias short circuit current detect threshold 00 = 600ua 01 = 1200ua 10 = 1800ua 11 = 2400ua these values are for avdd=3.3v and scale proportionally with avdd. 5:3 mdcthr [2:0] 000b micbias current detect threshold 000 = 200ua 001 = 350ua 010 = 500ua 011 = 650ua 100 = 800ua 101 = 950ua 110 = 1100ua 111 = 1200ua these values are for avdd=3.3v and scale proportionally with avdd. 2 mcd 0b micbias current and short circuit detect enable 0 = disabled 1 = enabled
production data wm8991 w pd, december 2008, rev 4.0 165 register address bit label default description 1 0b reserved - do not change 0 mbsel 0b microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd r59 (3bh) 15:0 0000h reserved - do not change r60 (3ch) pll (1) 15:8 00h reserved - do not change 7 sdm 0b enable pll integer mode 0 = integer mode 1 = fractional mode 6 prescale 0b divide mclk by 2 at pll input 0 = divide by 1 1 = divide by 2 5 0b reserved - do not change 4 0b reserved - do not change 3:0 plln [3:0] 8h integer (n) part of pll frequency ratio. use values greater than 5 and less than 13. r61 (3dh) pll (2) 15:8 00h reserved - do not change 7:0 pllk [15:8] 31h fractional (k) part of pll frequency ratio (most significant bits) r62 (3eh) pll (3) 15:8 00h reserved - do not change 7:0 pllk [7:0] 26h fractional (k) part of pll frequency ratio (least significant bits) r63 (3fh) to r116 (74h) reserved r117 (75h) access control 15:2 0000h reserved - do not change 1 ext_access_ena 0b ext ended register map access 0 = disabled 1 = enabled 0 0b reserved - do not change r118 (76h) to r121 (79h) reserved r122 (7ah) extended adc control 15 adcl_adcr_link 0b 0 = adc sync disabled 1 = adc sync enabled 14:0 2003h reserved - do not change r123 (7bh) to r127 (7fh) reserved
wm8991 production data w pd, december 2008, rev 4.0 166 digital filter characteristics parameter test conditions min typ max unit adc filter passband +/- 0.05db 0 0.454 fs -6db 0.5fs passband ripple +/- 0.05 db stopband 0.546s stopband attenuation f > 0.546 fs -60 db dac normal filter passband +/- 0.03db 0 0.454 fs -6db 0.5 fs passband ripple 0.454 fs +/- 0.03 db stopband 0.546 fs stopband attenuation f > 0.546 fs -50 db dac sloping stopband filter passband +/- 0.03db 0 0.25 fs +/- 1db 0.25 fs 0.454 fs -6db 0.5 fs passband ripple 0.25 fs +/- 0.03 db stopband 1 0.546 fs 0.7 fs stopband 1 attenuation f > 0.546 fs -60 db stopband 2 0.7 fs 1.4 fs stopband 2 attenuation f > 0.7 fs -85 db stopband 3 1.4 fs stopband 3 attenuation f > 1.4 fs -55 db dac filters adc filters mode group delay mode group delay normal 18 / fs normal 18 / fs sloping stopband 18 / fs
production data wm8991 w pd, december 2008, rev 4.0 167 adc filter responses -140 -120 -100 -80 -60 -40 -20 0 20 0.00 0.25 0.50 0.75 frequency (fs) -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.00 0.25 frequency (fs) figure 90 adc digital filter frequency response figure 91 adc digital filter ripple adc high pass filter responses ma gnitude( db) 1 2.6923 7.2484 19.515 52.54 141.45 380.83 1.0253k 2.7605k 7.432k 20.009k -11.736 -10.562 -9.3883 -8.2145 -7.0407 -5.8669 -4.6931 -3.5193 -2.3455 -1.1717 2.1246m hpf_response.res magnitude(db) hpf_response2.res magnitude(db) hpf_response2.res#1 magnitude(db) 2 5.0248 12.624 31.716 79.683 200. 19 502.96 1.2636k 3.1747k 7.9761k 20.039k -83.352 -75.017 -66.682 -58.347 -50.012 -41.677 -33.342 -25.007 -16.672 -8.3373 -2.3338m figure 92 adc digital high pass filter frequency response (48khz, hi-fi mode, adc_hpf_cut[1:0]=00) figure 93 adc digital high pass filter ripple (48khz, voice mode, adc_hpf_cut=01, 10 and 11)
wm8991 production data w pd, december 2008, rev 4.0 168 dac filter responses dac stopband attenuation the dac digital filter type is selected by the dac_sb_filt register bit as shown in table 91. register address bit label default description r10 (0ah) 8 dac_sb_fi lt 0b selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode table 91 dac filter selection magnitude(db) -150 -130 -110 -90 -70 -50 -30 -10 10 0 0.5 1 1.5 2 2.5 3 frequency (fs) magnitude(db) -0.005 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) figure 94 dac digital filter frequency response (normal mode) figure 95 dac digital filter ripple (normal mode) magnitude(db) -150 -130 -110 -90 -70 -50 -30 -10 10 0 0.5 1 1.5 2 2.5 3 frequency (fs) magnitude(db) -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) figure 96 dac digital filter frequency response (sloping stopband mode) figure 97 dac digital filter ripple (sloping stopband mode)
production data wm8991 w pd, december 2008, rev 4.0 169 de-emphasis filter responses magnitude(db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 frequency (hz) magnitude(db) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 frequency (hz) figure 98 de-emphasis digital filter response (32khz) figure 99 de-emphasis error (32khz) magnitude(db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 25000 frequency (hz) magnitude(db) -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 5000 10000 15000 20000 25000 frequency (hz) figure 100 de-emphasis digital filter response (44.1khz) figure 101 de-emphasis error (44.1khz) magnitude(db) -12 -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 25000 30000 frequency (hz) magnitude(db) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0 5000 10000 15000 20000 25000 30000 frequency (hz) figure 102 de-emphasis digital filter response (48khz) figure 103 de-emphasis error (48khz)
wm8991 production data w pd, december 2008, rev 4.0 170 applications information recommended external components notes: 1. wolfson recommend using a single, common ground reference. where this is not possible care should be taken to optimise split ground configuration for audio performance. 2. supply decoupling capacitors on dcvdd, dbvdd, spkvdd, hpvdd and avdd should be positioned as close to the wm8991 as possible. values indicat ed are minimum requirements. 3. capacitor types should be carefully chosen. capacitors with very low esr are recommended for optimum performance. 4. the loudspeaker should be connected as close as possible to t he wm8991. when this is not possible, filtering should be place d on the speaker outputs close to the wm8991. 5. the 2k2 micbias resistors on each of the mic inputs are typi cal values and will be suitable for many electret type microphon es. however, it is recommended that engineers refer to individual micr ophone specifications prior to finalising the value of this c omponent. wm8991 avdd dcvdd spkvdd hpvdd dbvdd mode sdin sclk csb/addr mclk dacdat daclrc bclk adclrc/gpio1 adcdat gpio5/dacdat2 gpio4/daclrc2 gpio3/bclk2 gpio6/adclrcb gpio2/mclk2 lin1 lin4/rxn lin3/gpi7 lin2 rin1 rin4/rxp rin3/gpi8 rin2 agnd hpgnd spkgnd dgnd micbias vmid lop lon rop ron spkp spkn out3 out4 lout rout bb (voice codec) 1 f 1 f 1 f 1 f line outputs 1 f 1 f 220 f 220 f 8 ohm loudspeaker 16 or 32 ohm ear speaker 16 or 32 ohm headphones 4.7 f 4.7 f 4.7 f control interface (2, 3 or 4-wire via gpio) audio interface gpio 4.7 f 4.7 f 0.1 f 0.1 f vbatt dvdd avdd 1 f 1 f 1 f 1 f 1 f 1 f line input (fm radio) line input (melody chip) micbias micbias 2k2 2k2 headset mic handset mic agnd
production data wm8991 w pd, december 2008, rev 4.0 171 speaker selection for filterless operation, it is important to select a speaker with appropriate internal inductance. the internal inductance and the speaker's load resistance create a low-pass filter with a cut-off frequency of: f c = r l / 2 l e.g. for an 8 speaker and required cut-off frequency of 20khz, the speaker should be chosen to have an inductance of: l = r l / 2 f c = 8 / 2 * 20khz = 64 h 8 speakers typically have an inductance in the range 20 h to 100 h. care should be taken to ensure that the cut-off frequency of the speaker's internal filtering is low enough to prevent speaker damage. the class d outputs of the wm8991 operate at much higher frequencies than is recommended for most speakers, and the cut-off frequency of the filter should be low enough to protect the speaker. figure 104 speaker equivalent circuit pcb layout considerations the efficiency of the speaker drivers is affected by the series resistance between the wm8991 and the speaker (e.g. inductor esr) as shown in figure 105. this resistance should be as low as possible to maximise efficiency. figure 105 speaker connection losses
wm8991 production data w pd, december 2008, rev 4.0 172 the distance between the wm8991 and the speakers should be kept to a minimum to reduce series resistance, and also to reduce emi. further reductions in emi can be achieved by additional passive filtering and/or shielding as shown in figure 106. when additional passive filtering is used, low esr components should be chosen to minimise series resistance between the wm8991 and the speaker, maximising efficiency. lc passive filtering will usually be effective at reducing emi at frequencies up to around 30mhz. to reduce emissions at higher frequencies, ferrite beads placed as close to the device as possible will be more effective. figure 106 emi reduction techniques
production data wm8991 w pd, december 2008, rev 4.0 173 package dimensions
wm8991 production data w pd, december 2008, rev 4.0 174 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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